Display device

ABSTRACT

A driver circuit portion of a display device has a function in which image signals are written to a selected pixel successively so as to display an image on a screen and a function in which writing operation of an image signal is stopped and a transistor is turned off so as to maintain one image written to the screen when the one image is continuously displayed on the screen. Such functions are achieved by a transistor whose off current per micrometer in channel width is reduced to an extremely low value that is lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.

TECHNICAL FIELD

One embodiment of the present invention relates to a display device which includes field-effect transistors each including an oxide semiconductor.

BACKGROUND ART

Liquid crystal display devices are widely used for display devices ranging from large-sized display devices such as television receivers to small-sized display devices such as mobile phones. Therefore, the development of liquid crystal display devices is intended to achieve cost reduction or to provide high-value added liquid crystal display devices. In recent years in particular, there has been a growing interest in global environment and thus, the development of liquid crystal display devices consuming less power has attracted attention.

As an example of a method for reducing power consumption sufficiently as well as satisfying the basic display qualities such as brightness and contrast, a driving method of a display device in which a scanning period and a non-scanning period which is longer than the scanning period are provided has been disclosed (see Patent Document 1). Specifically, in the above driving method of a display device, all data signal lines are electrically disconnected from a data signal driver in an inactive period where all scan lines and data signal lines are not selected, whereby a high-impedance state is made.

REFERENCE

-   [Patent Document 1] Japanese Published Patent Application No.     2001-312253

DISCLOSURE OF INVENTION

For example, pixels in a liquid crystal display device each includes a transistor which controls an input of an image signal, a liquid crystal element to which voltage corresponding to the input image signal is applied, and a storage capacitor which holds the voltage applied to the liquid crystal element. The liquid crystal element contains a liquid crystal material whose alignment is changed in accordance with voltage applied. By controlling the alignment of the liquid crystal material, display of each pixel is controlled.

In the liquid crystal display device disclosed in Patent Document 1, an image signal is not input, in an inactive period, to each pixel included in a pixel portion. That is, the off state of a transistor which controls an input of an image signal is kept for a long period of time while an image signal is held in each pixel. Thus, the influence on display of each pixel due to leakage of an image signal through the transistor becomes apparent. Specifically, voltage applied to the liquid crystal element is reduced, whereby display degradation (change) of the pixel including the liquid crystal element becomes apparent.

Further, the amount of leakage of an image signal through the transistor varies depending on operation temperature of the transistor. Specifically, the amount of leakage of an image signal through the transistor is increased along with an increase in the operation temperature. Therefore, it is difficult for the liquid crystal display device disclosed in Patent Document 1 to maintain uniform display quality when the liquid crystal display device is used in the outdoors where environments vary widely.

Thus, an object of an embodiment of the present invention is to reduce consumed power and to suppress display degradation (reduction in display quality) in a liquid crystal display device. An object of an embodiment of the present invention is to provide a liquid crystal display device whose display degradation (reduction in display quality) caused by an external factor such as temperature is suppressed.

Further, an embodiment of the present invention is to achieve the aforementioned objects by use of a transistor whose channel formation region is formed using an oxide semiconductor layer for a transistor provided in each pixel. Note that it is preferable that the oxide semiconductor layer be highly purified by removing impurities (hydrogen, water, or the like) serving as electron donors (donors) as much as possible. A transistor whose channel formation region is formed using such an oxide semiconductor layer enables the off current per micrometer in channel width to be reduced to an extremely low value that is lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.

Note that the band gap of the oxide semiconductor layer is 2.0 eV or more, preferably 2.5 eV or more, still preferably 3.0 eV or more. In addition, an increase in the purity of the oxide semiconductor layer allows the conductivity of the oxide semiconductor layer to be as close to intrinsic as possible. Thus, in the oxide semiconductor layer, generation of carriers due to thermal excitation can be reduced. As a result, an increase in the off current along with an increase in the operation temperature of a transistor whose channel formation region is formed using the oxide semiconductor layer can be reduced.

As in one mode of a transistor including the above-described oxide semiconductor, parts of source and drain electrodes are formed using metal nitride. A gate electrode of the transistor may be provided below the oxide semiconductor layer (on the substrate side) or above the oxide semiconductor layer (on the side opposite to the substrate side). Alternatively, the gate electrodes may be provided above and below the oxide semiconductor layer. In any case, the gate electrode may be provided with an insulating layer interposed between the gate electrode and the oxide semiconductor layer. In addition to the characteristics of the transistor in an off state, the transistor in an on state has the following characteristics. The maximum value of the field-effect mobility is higher than or equal to 5 cm²/Vsec, preferably in the range of 10 cm²/Vsec to 150 cm²/Vsec. With use of such a transistor which can operate at high speed, writing operation or the like can be performed rapidly even when the density of pixel becomes high.

One embodiment of the present invention is a display device provided with a display panel which includes a pixel portion and a driver circuit portion. In the pixel portion, pixels are arranged in matrix, the pixels each including one or more units each of which includes a transistor in which an oxide semiconductor layer is provided to overlap with a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which is connected to a source or drain side of the transistor and drives liquid crystal, a counter electrode provided to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. The driver circuit portion is configured to drive the pixel portion and display an image on a screen. Moreover, the driver circuit portion has a function to stop a writing operation of an image signal and turn the transistor off so as to maintain one image written to the screen when the one image is continuously displayed on the screen, as well as a function to write an image signal to a selected pixel successively so as to display an image on the screen. Such a function can be achieved by use of the above transistor.

One embodiment of the present invention is a display device provided with a display panel which includes a pixel portion and a driver circuit portion. In the pixel portion, pixels are arranged in matrix, the pixels each including one or more units each of which includes a transistor in which an oxide semiconductor layer is provided to overlap with a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which is connected to a source or drain side of the transistor and drives liquid crystal, a counter electrode provided to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. The driver circuit portion is configured to drive the pixel portion and display an image on a screen. The driver circuit portion has a function to select two operation modes. In one of the operation mode, a writing operation is performed by writing an image signal to a selected pixel successively so as to display an image on the screen. In the other operation mode, the wiring operation of an image signal is stopped so as to maintain one image written to the screen when the one image is continuously displayed on the screen. Such a function can be achieved by use of the above transistor.

In a liquid crystal display device which is an embodiment of the present invention, a transistor whose channel formation region is formed using an oxide semiconductor layer is used as the transistor provided in each pixel. When the oxide semiconductor layer is highly purified, the off current value per micrometer in channel width of the transistor can be lower than 10 zA/μm at room temperature and, when temperature is 85° C., lower than 100 zA/μm. Therefore, the amount of leakage of an image signal through the transistor can be reduced. That is, display degradation (change) which occurs when writing frequency of an image signal to a pixel including the transistor is reduced can be suppressed. Thus, consumed power can be reduced and display degradation (reduction in display quality) can be suppressed in the liquid crystal display device.

Further, a pixel including a transistor with extremely low off current can keep a constant state (a state where an image signal is written) and thus operates stably even in the case where a still image is displayed. In such a case, in the transistor, an increase in off current which accompanies an increase in operation temperature is extremely small; thus, the influence on leakage of an image signal in the pixel due to an external factor such as temperature can be reduced. In other words, in the liquid crystal display device, display degradation (reduction in display quality) can be suppressed even when a state where an image signal is written is kept and a still image is displayed in the outdoors where environments vary widely.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating a structure of a liquid crystal display device according to Embodiment 1.

FIG. 2 is a block diagram illustrating a structure of a liquid crystal display device according to Embodiment 1.

FIG. 3 is a block diagram illustrating a structure of a pixel and a driver circuit portion in a liquid crystal display device according to Embodiment 1.

FIG. 4 is a timing chart describing operation of a liquid crystal display device according to Embodiment 1.

FIGS. 5A and 5B are timing charts describing operation of a display control circuit in a liquid crystal display device according to Embodiment 1.

FIG. 6 is a diagram schematically showing writing frequency of an image signal in a period during which a moving image is displayed and a period during which a still image is displayed.

FIGS. 7A and 7B illustrate a structure of a television receiver according to Embodiment 2.

FIGS. 8A and 8B illustrate a structure of a monitor according to Embodiment 2.

FIGS. 9A to 9C illustrate a structural example of a backlight of a liquid crystal display device.

FIGS. 10A to 10C illustrate a structural example of a backlight of a liquid crystal display device.

FIGS. 11A to 11D each illustrate an example of a transistor which can be applied to a liquid crystal display device.

FIGS. 12A to 12E illustrate an example of a transistor including an oxide semiconductor layer and a manufacturing method thereof.

FIG. 13 is a graph showing an example of V_(g)-I_(d) characteristics of a transistor including an oxide semiconductor.

FIG. 14 is a graph showing off-state characteristics in V_(g)-I_(d) characteristics of a transistor including an oxide semiconductor.

FIG. 15 is a graph showing the relation between source-drain voltage V and off current I.

FIGS. 16A and 16B illustrate an example of an electronic book reader according to the present invention.

FIG. 17 illustrates an example of a computer according to the present invention.

FIG. 18 is a plane view illustrating an example of a pixel in a liquid crystal display device.

FIG. 19 is a cross-sectional view illustrating an example of a pixel in a liquid crystal display device.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described using the accompanying drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the purpose and the scope of the present invention. Therefore, this invention disclosed in this specification is not interpreted as being limited to the description of embodiments below.

When the embodiments are described with reference to drawings, the same reference numerals may be used to denote the same components among different drawings. Note that components illustrated in the drawings, that is, a thickness or a width of a layer, a region, or the like, a relative position, and the like are exaggerated in some cases for clarification in description of the embodiments.

(Embodiment 1)

In this embodiment, one embodiment of a liquid crystal display device and a driving method thereof with low power consumption will be described with reference to FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIGS. 5A and 5B, and FIG. 6.

Components of a liquid crystal display device 100 described in this embodiment are illustrated in a block diagram of FIG. 1. The liquid crystal display device 100 includes an image processing circuit 110, a power supply 116, a display control circuit 113, and a display panel 120. In the case of a transmissive liquid crystal display device or a transflective liquid crystal display device, a backlight portion 130 units is further provided as a light source.

An image signal (image signal Data) is supplied to the liquid crystal display device 100 from an external device which is connected to the liquid crystal display device 100. Note that power supply potential (high power supply potential V_(dd), low power supply potential V_(ss), and common potential V_(com)) is supplied by turning on the power supply 116 of the liquid crystal display device and starting supplying power, and a control signal (start pulse SP and clock signal CK) is supplied by the display control circuit 113.

Note that the high power supply potential V_(dd) is a potential higher than reference potential, and the low power supply potential V_(ss) is a potential lower than or equal to the reference potential. It is preferable that both the high power supply potential V_(dd) and the low power supply potential V_(ss) have such a level as to allow the transistor to operate. The high power supply potential V_(dd) and the low power supply potential V_(ss) are collectively referred to as a power supply voltage in some cases.

The common potential V_(com) may be any potential as long as it serves as a fixed potential and a reference with respect to the potential of an image signal supplied to a pixel electrode. For example, the common potential may be ground potential.

The image signal Data may be appropriately inverted corresponding to dot inversion driving, source line inversion driving, gate line inversion driving, frame inversion driving, or the like to be supplied to the liquid crystal display device 100. In the case where the image signal is an analog signal, it may be converted to a digital signal through an A/D converter or the like to be supplied to the liquid crystal display device 100.

In this embodiment, the common potential V_(com) which is a fixed potential is supplied from the power supply 116 to one of electrodes of a common electrode 128 and one of electrodes of a capacitor 210 through the display control circuit 113.

The display control circuit 113 supplies an image signal (Data), a control signal (specifically, a signal for controlling a supply or a stop of the supply of a control signal such as a start pulse SP and a clock signal CK), and power supply potential (high power supply potential V_(dd), low power supply potential V_(ss), and common potential V_(com)) to the display panel 120.

The image processing circuit 110 analyzes, calculates, and processes an input image signal (image signal Data), and then outputs the processed image signal together with a control signal to the display control circuit 113.

Specifically, the image processing circuit 110 analyzes the input image signal Data, determines whether the input image signal Data is for a moving image or a still image, and outputs a control signal including the determination result to the display control circuit 113. Further, the image processing circuit 110 captures a still image of one frame from the image signal Data including a moving image or a still image and outputs the captured image together with a control signal for indicating a still image to the display control circuit 113. Furthermore, the image processing circuit 110 outputs the input image signal Data and the above control signal to the display control circuit 113. Note that the above-described function is an example of functions which the image processing circuit 110 has, and a variety of image processing functions may be selected depending on usage of the display device.

Note that since an image signal which is converted to a digital signal is easily calculated (e.g., detection of a difference between image signals), in the case where an input image signal (image signal Data) is an analog signal, an A/D converter or the like is provided in the image processing circuit 110.

The display panel 120 includes a liquid crystal element 215 sandwiched between a pair of substrates (a first substrate and a second substrate), and a driver circuit portion 121 and a pixel portion 122 are provided over the first substrate. Further, the second substrate is provided with a common connection portion (also referred to as a common contact) and the common electrode 128 (also referred to as a counter electrode). Note that the first substrate and the second substrate are electrically connected to each other through the common connection portion, and the common connection portion may be provided over the first substrate.

A plurality of gate lines 124 (scan lines) and a plurality of source lines 125 (signal lines) are provided in the pixel portion 122 and a plurality of pixels 123 are provided in matrix so that the pixels are surrounded by the gate lines 124 and the source lines 125. Note that in the display panel illustrated in this embodiment, the gate lines 124 are extended from a gate line driver circuit 121A and the source lines 125 are extended from a source line driver circuit 121B.

Further, each pixel 123 includes a transistor 214 functioning as a switching element, a capacitor 210 connected to the transistor 214, and a liquid crystal element 215 connected to the transistor 214.

The liquid crystal element 215 controls transmission or non-transmission of light by an optical modulation action of liquid crystal. The optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal. An electric field direction applied to the liquid crystal differs depending on a liquid crystal material, a driving method, and an electrode structure and can be selected as appropriate. For example, in the case where a driving method in which an electric field is applied in a direction of a thickness of liquid crystal (a so-called perpendicular direction) is used, a pixel electrode and a common electrode are provided on the first substrate and the second substrate, respectively, so that the liquid crystal is interposed therebetween. In the case where a driving method in which an electric field is applied in an in-plane direction of a substrate (a so-called horizontal direction) to liquid crystal is used, a pixel electrode and a common electrode may be provided on the same surface as the liquid crystal. The pixel electrode and the common electrode may have a variety of opening patterns. There is no particular limitation on a liquid crystal material, a driving method, and an electrode structure in this embodiment as long as the liquid crystal element controls transmission or non-transmission of light by the optical modulation action.

In each transistor 214, a gate electrode is connected to one of the plurality of gate lines 124 provided in the pixel portion 122, one of source and drain electrodes is connected to one of the plurality of source lines 125, and the other of source and drain electrodes is connected to one of electrodes of the capacitor 210 and one of electrodes (pixel electrode) of the liquid crystal element 215.

As the transistor 214, a transistor whose off current is reduced is preferably used. When the transistor 214 whose off current is reduced is off, electrical charges accumulated in the capacitor 210 and the liquid crystal element 215 which are connected to the transistor 214 are less likely to leak through the transistor 214. In addition, a state in which a signal is written before the transistor 214 is turned off can be stably held until next signal is written. Thus, the pixel 123 can functions without the capacitor 210 connected to the transistor 214 whose off current is reduced.

With such a structure, the capacitor 210 can hold the voltage applied to the liquid crystal element 215. The electrode of the capacitor 210 may be connected to a capacitor line which is additionally provided.

The driver circuit portion 121 includes the gate line driver circuit 121A and the source line driver circuit 121B. The gate line driver circuit 121A and the source line driver circuit 121B are driver circuits for driving the pixel portion 122 including the plurality of pixels and each include a shift register circuit (also referred to as a shift register).

Note that the gate line driver circuit 121A and the source line driver circuit 121B may be formed over the same substrate as the pixel portion 122 or may be formed over a different substrate from the substrate where the pixel portion 122 is formed.

Note that high power supply potential V_(dd), low power supply potential V_(ss), a start pulse SP, a clock signal CK, and an image signal Data which are controlled by the display control circuit 113 are supplied to the driver circuit portion 121.

A terminal portion 126 is an input terminal which supplies predetermined signals (high power supply potential V_(dd), low power supply potential V_(ss), a start pulse SP, a clock signal CK, an image signal Data, common potential V_(com), and the like) which are output from the display control circuit 113, to the driver circuit portion 121.

The common electrode 128 is electrically connected to a common potential line which supplies common potential V_(com) controlled by the display control circuit 113 through the common connection portion.

As a specific example of the common connection portion, a conductive particle in which an insulating sphere is covered with a metal thin film is interposed between the common electrode 128 and the common potential line, whereby the common electrode 128 and the common potential line can be electrically connected to each other. Note that two or more common connection portions may be provided in the display panel 120.

In addition, the liquid crystal display device may include a photometry circuit. The liquid crystal display device provided with the photometry circuit can detect brightness of the environment where the liquid crystal display device is set. Thus, the display control circuit 113 to which the photometry circuit is connected can control a driving method of a light source such as a backlight or a sidelight in accordance with a signal input from the photometry circuit.

The backlight portion 130 includes a backlight control circuit 131 and a backlight 132. The backlight 132 may be selected as appropriate, depending on the usage of the liquid crystal display device 100. The liquid crystal display device 100 is provided with a lighting unit for lighting, and a light-emitting diode (LED) or the like may be used as a light source of the lighting unit. For the backlight 132, a light-emitting element emitting white light (such as an LED) can be provided, for example. The backlight control circuit 131 is supplied with a backlight signal which controls a backlight and a power supply potential from the display control circuit 113.

Note that when color display is performed, display can be performed using a color filter. In addition, another optical film (such as a polarizing film, a retardation film, or an anti-reflection film) can be used. A light source such as a backlight used for a transmissive liquid crystal display device or a transflective liquid crystal display device may be selected in accordance with usage of the liquid crystal display device 100, and for example, a cold cathode tube, a light-emitting diode (LED) or the like can be used. Further, a surface light source may be formed using a plurality of LED light sources, a plurality of electroluminescent (EL) light sources, or the like. As the surface light source, three or more kinds of LEDs may be used and an LED emitting white light may be used. Note that the color filter is not provided in the case where RGB light-emitting diodes or the like are arranged in a backlight and a successive additive color mixing method (a field sequential method) in which color display is performed by time division is employed.

Next, a driving method of the liquid crystal display device illustrated in FIG. 1 will be described with reference to FIG. 2, FIG. 3, FIG. 4, FIGS. 5A and 5B, and FIG. 6. The driving method of the liquid crystal display device described in this embodiment is a display method in which the frequency of rewriting in the display panel varies depending on display images. Specifically, in the case where image signals in a series of frames are different from each other (i.e., a moving image is displayed), a display mode in which an image signal is written to every frame is employed. On the other hand, in the case where image signals in a series of frames have the same image (still image), a display mode for a still image is employed as follows: image signals are prevented to be written or the writing frequency is extremely reduced in a period during which the same image is being displayed; the voltage applied to the liquid crystal element is kept by setting potentials of the pixel electrode and the common electrode in a floating state; and accordingly a still image is displayed without an additional supply of potential.

The liquid crystal display device combines a moving image and a still image and displays images on the screen. Note that by switching of a plurality of different images which are time-divided into a plurality of frames at high speed, the images are recognized as a moving image by human eyes. Specifically, by switching of images at least 60 times (60 frames) per second, the images are recognized as a moving image with less flicker by human eyes. In contrast, unlike a moving image and a partial moving image, a still image is an image which does not change in a series of frame periods, for example, between an n-th frame and an (n+1)-th frame though a plurality of images which are time-divided into a plurality of frame periods are switched at high speed.

The liquid crystal display device according to one embodiment of the present invention realizes different display modes, a moving image display mode when a moving image is displayed and a still image display mode when a still image is displayed. Note that in this specification, an image displayed in a still image mode is also called a static image.

Next, a structure of the liquid crystal display device 100 of this embodiment is described with reference to a block diagram of FIG. 2. The liquid crystal display device 100 is an example of a transmissive liquid crystal display device or a transflective liquid crystal display device which performs display on the pixel by utilizing transmission or non-transmission of light, which includes the image processing circuit 110, the power supply 116, the display panel 120, and the backlight portion 130. Note that in a reflective liquid crystal display device, external light is used as a light source, and accordingly the backlight portion 130 does not need to be provided.

The liquid crystal display device 100 is supplied with an image signal (image signal Data) from an external device connected thereto. Note that the power supply potential (high power supply potential V_(dd), low power supply potential V_(ss), and common potential V_(com)) is supplied when the power supply 116 is turned on to start supplying power, and the control signal (start pulse SP and clock signal CK) is supplied from the display control circuit 113.

Next, a structure of the image processing circuit 110 and a procedure in which the image processing circuit 110 processes signals are described with reference to FIG. 2 as an example. Note that the image processing circuit 110 illustrated in FIG. 2 is just one mode and this embodiment is not limited to this structure.

The image processing circuit 110 illustrated in FIG. 2 analyzes image signals which are successively input and determines whether the input image signal is for a moving image or a still image. When the input operation of image signals (image signal Data) is changed from inputting a moving image signal to inputting a still image signal, the image processing circuit 110 captures a still image and outputs the captured still image together with a control signal for indicating a still image to the display control circuit 113. When the input operation of image signals (image signal Data) is changed from inputting a still image signal to inputting a moving image signal, the image processing circuit 110 outputs an image signal including a moving image together with a control signal for indicating a moving image to the display control circuit 113.

The image processing circuit 110 includes a memory circuit 111, a comparison circuit 112, and a selection circuit 115. The image processing circuit 110 generates a display panel image signal and a backlight signal from the input digital image signal Data. The display panel image signal is an image signal which controls the display panel 120 and the backlight signal is a signal which controls the backlight portion 130.

The memory circuit 111 includes a plurality of frame memories for storing image signals of a plurality of frames. There is no particular limitation on the number of frame memories included in the memory circuit 111 as long as the image signals of a plurality of frames can be stored. Note that the frame memory may be formed using a memory element such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

Note that the number of frame memories is not particularly limited to the certain number as long as each frame memory stores an image signal for one frame period. Further, the image signals stored in the frame memories are selectively read by the comparison circuit 112 and the display control circuit 113. Note that a frame memory 111 b in the drawing is schematically illustrated as a memory region of one frame.

The comparison circuit 112 is a circuit which selectively reads out image signals in a series of frame periods stored in the memory circuit 111, compares the image signals in a series of frames for each pixel, and detects a difference thereof.

Note that in this embodiment, operation of the display control circuit 113 and the selection circuit 115 is determined depending on whether or not a difference between image signals is detected in a series of frames. In the case where the comparison circuit 112 detects a difference between frames in any pixel (in the case of difference “yes”), the comparison circuit 112 determines that the image signals are not still image signals and that the series of frame periods where a difference is detected is for displaying a moving image.

On the other hand, in the case where a difference is not detected in all pixels by the comparison between image signals by the comparison circuit 112 (in the case of difference “no”), the comparison circuit 112 determines that the series of frame periods where a difference is not detected are for displaying a still image. That is, the comparison circuit 112 determines whether image signals in a series of frame periods are moving image signals or still image signals by detecting whether or not there is a difference between the image signals.

Note that the detection by the comparison may be conducted on such a condition that the result of difference “yes” is determined when the difference exceeds a certain level. Note that a difference detected by the comparison circuit 112 may be determined by the absolute value of the difference.

Further, in this embodiment, the comparison circuit 112 provided in the liquid crystal display device 100 detects a difference between image signals in a series of frame periods, thereby determining whether the image is a moving image or a still image; however, a structure in which a signal indicating whether an image is a moving image or a still image may be supplied from the outside.

The selection circuit 115 includes a plurality of switches, for example, switches formed using transistors. In the case where the comparison circuit 112 detects a difference in a series of frames, that is, in the case where an image is a moving image, the selection circuit 115 selects an image signal of a moving image from the frame memories in the memory circuit 111 and outputs the image signals to the display control circuit 113.

Note that in the case where the comparison circuit 112 does not detect a difference in a series of frames, that is, in the case where an image is a still image, the selection circuit 115 does not output the image signal from the frame memories in the memory circuit 111 to the display control circuit 113. Image signals are not output from the frame memories to the display control circuit 113, which enables power consumed in the liquid crystal display device to be reduced.

Note that in the liquid crystal display device of this embodiment, a mode performed in such a way that the comparison circuit 112 determines the image signal as a still image is described as a still-image display mode, and a mode performed in such a way that the comparison circuit 112 determines the image signal as a moving-image is described as a moving image display mode.

The display control circuit 113 supplies, to the display panel 120, an image signal selected by the selection circuit 115, a control signal (specifically, a signal for controlling switching of supply or stop of the supply of the control signals such as start pulse SP and clock signal CK), and the power supply potential (high power supply potential V_(dd), low power supply potential V_(ss), and common potential V_(com)). In addition, the display control circuit 113 supplies, to the backlight portion 130, a backlight control signal (specifically, a signal for controlling on/off of the backlight which is conducted on the backlight control circuit 131).

Note that the image processing circuit described in this embodiment may have a function of switching display modes. The function of switching display modes is a function of switching between a moving-image display mode and a still-image display mode in such a manner that a user selects an operation mode of the liquid crystal display device by hand or using an external connection device.

The selection circuit 115 can output the image signal to the display control circuit 113 in accordance with a signal input from the mode-switching circuit.

For example, when a mode-switching signal is input to the selection circuit 115 from the mode-switching circuit while the liquid crystal display device operates in a still-image display mode, even in a state where the comparison circuit 112 does not detect the difference between the image signals in a series of frame periods, the selection circuit 115 can conduct a mode in which input image signals are sequentially output to the display control circuit 113, that is, a moving-image display mode. When a mode-switching signal is input to the selection circuit 115 from the mode-switching circuit while the liquid crystal display device operates in a moving-image display mode, even in a state where the comparison circuit 112 detects the difference between the image signals in a series of frame periods, the selection circuit 115 can conduct a mode in which only an image signal of one selected frame is output, that is, a still-image display mode. As a result, in the liquid crystal display device of this embodiment, one frame among moving images is displayed as a still image.

Further, in the case where the liquid crystal display device includes a photometric circuit, when the photometric circuit detects brightness and finds that the liquid crystal display device is used in a dim environment, the display control circuit 113 controls light of the backlight 132 to have high intensity, so that favorable visibility of a display screen is secured. In contrast, when it is found that the liquid crystal display device is used under extremely bright external light (e.g., under direct sunlight outdoors), the display control circuit 113 controls light of the backlight 132 to have lower intensity, so that power consumed by the backlight 132 is reduced.

In this embodiment, the display panel 120 includes a switching element 127 in addition to the pixel portion 122. In this embodiment, the display panel 120 includes the first substrate and the second substrate. The driver circuit portion 121, the pixel portion 122, and the switching element 127 are provided over the first substrate.

Moreover, the pixel 123 includes the transistor 214 functioning as a switching element, the capacitor 210 connected to the transistor 214, and the liquid crystal display element 215 connected to the transistor 214 (see FIG. 3).

A transistor whose off current is reduced is preferably used for the transistor 214. When the transistor 214 is off, electrical charges accumulated in the capacitor and the liquid crystal element 215 which are connected to the transistor 214 whose off current is reduced are less likely to leak through the transistor 214, and a state where a signal is written before the transistor 214 is off can be held for a long time.

In this embodiment, a liquid crystal is controlled by a vertical electric field generated between the pixel electrode provided over the first substrate and the common electrode provided on the second substrate which faces the first substrate.

As an example of liquid crystal applied to the liquid crystal element, the following can be given: nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low-molecular liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, anti-ferroelectric liquid crystal, main-chain liquid crystal, side-chain high-molecular liquid crystal, banana-shaped liquid crystal, and the like.

In addition, examples of a driving method of liquid crystal include a TN (twisted nematic) mode, an STN (super twisted nematic) mode, an OCB (optically compensated birefringence) mode, an ECB (electrically controlled birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (anti-ferroelectric liquid crystal) mode, a PDLC (polymer dispersed liquid crystal) mode, a PNLC (polymer network liquid crystal) mode, a guest-host mode, and the like.

The switching element 127 supplies the common potential V_(com) to the common electrode 128 in accordance with a control signal which the display control circuit 113 outputs. As the switching element 127, a transistor can be used. A gate electrode of the transistor and one of a source electrode and a drain electrode of the transistor may be connected to the display control circuit 113 so that the common potential V_(com) is supplied from the display control circuit 113 to the one of the source electrode and the drain electrode of the transistor through the terminal portion 126. The other of the source electrode and the drain electrode of the transistor may be connected to the common electrode 128. Note that the switching element 127 may be formed over the same substrate as the driver circuit portion 121 and the pixel portion 122 or may be formed over a different substrate from the substrate where the driver circuit portion 121 and the pixel portion 122 are formed.

A transistor whose off current is reduced is used as the switching element 127, whereby a reduction over time in the voltage applied to both terminals of the liquid crystal element 215 can be suppressed.

A terminal connected to the source electrode or the drain electrode of the switching element 127 and the common electrode 128 are electrically connected to each other through the common connection portion.

Of the switching element 127 which is a transistor as one mode of a switching element, one of the source electrode and the drain electrode is connected to a terminal 126B through the common connection portion, and the other of the source electrode and the drain electrode is connected to the other electrode of the capacitor 210 and the other electrode of the liquid crystal element 215 which are not connected to the transistor 214. Further, the gate electrode of the switching element 127 is connected to a terminal 126A.

Next, signals supplied to the pixels are described with reference to an equivalent circuit diagram of the liquid crystal display device illustrated in FIG. 3 and a timing chart shown in FIG. 4.

A clock signal GCK and a start pulse GSP which the display control circuit 113 supplies to the gate line driver circuit 121A are shown in FIG. 4. In addition, a clock signal SCK and a start pulse SSP which the display control circuit 113 supplies to the source line driver circuit 121B are also shown. Note that waveform of the clock signals are shown in simple rectangular waves in FIG. 4 in order to describe timings of outputting the clock signals.

Further, high power supply potential V_(dd), potential of the source line 125 (potential of a Data line), potential of the pixel electrode, potential of the terminal 126A, potential of the terminal 126B, and potential of the common electrode are shown in FIG. 4.

In FIG. 4, a period 1401 corresponds to a period during which image signals for displaying a moving image are written. In the period 1401, image signals and common potential are supplied to each pixel of the pixel portion 122 and the common electrode.

Further, a period 1402 corresponds to a period during which a still image is displayed. In the period 1402, the supply of image signals to each pixel of the pixel portion 122 and the supply of the common potential to the common electrode are stopped. Note that a structure of FIG. 4 shows that each signal is supplied so that the driver circuit portion stops operating during the period 1402; however, it is preferable to employ a structure in which image signals are regularly written depending on the length of the period 1402 and the refresh rate so as to prevent deterioration of a still image.

First, a timing chart of the period 1401 is described. In the period 1401, the clock signal GCK is always supplied as a clock signal and a pulse corresponding to vertical synchronization frequency is supplied as the start pulse GSP. Moreover, in the period 1401, the clock signal SCK is always supplied as a clock signal and a pulse corresponding to one gate selection period is supplied as the start pulse SSP.

The image signal Data is supplied to the pixels in each row through the source line 125 and potential of the source line 125 is supplied to the pixel electrode in accordance with potential of the gate line 124.

The display control circuit 113 supplies potential which makes the switching element 127 turn on to the terminal 126A of the switching element 127 and common potential to the common electrode through the terminal 126B.

On the other hand, the period 1402 is a period during which a still image is displayed. A timing chart of the period 1402 is described. In the period 1402, the supply of the clock signal GCK, the start pulse GSP, the clock signal SCK, and the start pulse SSP is stopped. Further, in the period 1402, the supply of the image signal Data to the source line 125 is stopped. In the period 1402 during which the supply of the clock signal GCK and the start pulse GSP is stopped, the transistor 214 is off, and the potential of the pixel electrode becomes in a floating state.

In addition, the display control circuit 113 supplies potential to the terminal 126A of the switching element 127 to bring the switching element 127 into an off state, so that the potential of the common electrode becomes in a floating state.

In the period 1402, the potential of both terminals of the liquid crystal element 215, that is, the pixel electrode and the common electrode, becomes in a floating state, so that a still image can be displayed without additional potential supply.

The supply of a clock signal and a start pulse to the gate line driver circuit 121A and the source line driver circuit 121B is stopped, so that low power consumption can be achieved.

In particular, a transistor whose off current is reduced is used for the transistor 214 and the switching element 127, whereby a reduction over time in the voltage applied to both terminals of the liquid crystal element 215 can be suppressed.

Next, operation of the display control circuit in a period during which a displayed image is switched to a still image from a moving image (a period 1403 in FIG. 4) and in a period during which a displayed image is switched to a moving image from the still image (a period 1404 in FIG. 4) is described with reference to FIGS. 5A and 5B. FIGS. 5A and 5B show high power supply potential V_(dd), a clock signal (here, GCK), a start pulse signal (here, GSP), and potential of the terminal 126A which the display control circuit outputs.

The operation of the display control circuit in the period 1403 during which a displayed image is switched to a still image from a moving image is shown in FIG. 5A. The display control circuit stops the supply of the start pulse GSP (E1 in FIG. 5A, a first step). Next, the supply of a plurality of clock signals GCK is stopped after the pulse output reaches the last stage of the shift register (E2 in FIG. 5A, a second step). Next, the power supply voltage is changed from the high power supply potential V_(dd) to the low power supply potential V_(ss) (E3 in FIG. 5A, a third step). Then, the potential of the terminal 126A varies to potential which brings the switching element 127 into an off state (E4 in FIG. 5A, a fourth step).

Through the above steps, the supply of the signals to the driver circuit portion 121 can be stopped without a malfunction of the driver circuit portion 121. A malfunction generated of when the displayed image is switched from a moving image to a still image causes a noise, and the noise is held as a still image. Thus, a liquid crystal display device mounted with a display control circuit with less malfunctions can display a still image with less image deterioration.

Next, the operation of the display control circuit in the period 1404 during which a displayed image is switched to a moving image from the still image is described with reference to FIG. 5B. The display control circuit makes the potential of the terminal 126A bring the switching element 127 into an on state (S1 in FIG. 5B, a first step). Next, the power supply voltage is changed from the low power supply potential V_(ss) to the high power supply potential V_(dd) (S2 in FIG. 5B, a second step). After high potential is applied in advance, a plurality of clock signals GCK are supplied (S3 in FIG. 5B, a third step). Next, the start pulse signal GSP is supplied (S4 in FIG. 5B, a fourth step).

Through the above steps, the supply of driving signals to the driver circuit portion 121 can restart without a malfunction of the driver circuit portion 121. When potentials of wirings are sequentially changed back to those at the time of displaying a moving image, the driver circuit portion can be driven without a malfunction.

In addition, the frequency of writing image signals in the period 601 during which a moving image is displayed and the period during which a still image is displayed is schematically shown in FIG. 6. In FIG. 6, “W” indicates a period during which an image signal is written, and “H” indicates a period during which the image signal is held. In addition, a period 603 indicates one frame period; however, the period 603 may be a different period.

As described above, in the liquid crystal display device of this embodiment, an image signal of a still image displayed during the period 602 is written in a period 604, and the image signal written in the period 604 is held during the periods included in the period 602 other than the period 604.

In the liquid crystal display device described in this embodiment, frequency of writing an image signal in a period during which a still image is displayed can be reduced. As a result, consumed power while a still image is displayed can be reduced.

In the case where a still image is displayed by rewriting the same image a plurality of times, switching of images can be seen, which might cause eye strain. In the liquid crystal display device of this embodiment, the frequency of writing image signals is reduced, whereby eye strain can be reduced.

Specifically, by using transistors whose off currents are reduced for each pixel and the switching element of the common electrode, the liquid crystal display device of this embodiment can provide a long period (time) of holding a voltage in a storage capacitor. As a result, the frequency of writing image signals can be drastically reduced, so that consumed power at the time of displaying a still image and eye strain can be significantly reduced.

(Embodiment 2)

In this embodiment, an example of an electronic device including the liquid crystal display device described in Embodiment 1 will be described.

FIG. 7A is an external view of a television receiver which is an electronic device. FIG. 7A illustrates a structure in which a housing 700 is mounted with a display module 701 manufactured using the display panel described in Embodiment 1 and is provided with a speaker 702, operation keys 703, an external connection terminal 704, an illuminance sensor 705, and the like.

The television receiver illustrated in FIG. 7A can display text information or a still image in addition to a moving image. A part of a display portion can be used for moving image display and the other part of the display portion can be used for still image display. Note that as still image display, an image of a character, a diagram, a symbol, a photograph, a pattern, or a painting or a combination of any of them is included. Alternatively, any of the above images which are colored is included as still image display.

FIG. 7B is a block diagram of a main structure of the television receiver. A television receiver 710 illustrated in FIG. 7B includes a tuner 711, a digital demodulation circuit 712, a video signal processing circuit 713, an audio signal processing circuit 714, a display adjustment circuit 715, a display control circuit 716, a display panel 717, a gate line driver circuit 718, a source line driver circuit 719, a speaker 720, and an image processing circuit 724.

The tuner 711 receives a video signal and an audio signal from an antenna 721. The digital demodulation circuit 712 demodulates a signal from the tuner 711 to a video signal and an audio signal of a digital signal. The video signal processing circuit 713 converts the video signal of a digital signal into a color signal corresponding to each color of red, green, and blue. The audio signal processing circuit 714 converts the audio signal of a digital signal into a signal which is output as the sound from the speaker 720. The display adjustment circuit 715 receives control information on a receiving station (receiving frequency) and sound volume from an external input portion 722 and transmits the signal to the tuner 711 or the audio signal processing circuit 714.

The display control circuit 716, the display panel 717, the gate line driver circuit 718, the source line driver circuit 719, and the image processing circuit 724 correspond to the display control circuit 113, the display panel 120, the gate line driver circuit 121A, the source line driver circuit 121B, and the image processing circuit 110 described in Embodiment 1 respectively. That is, a structure of a dotted line portion 723 corresponds to the liquid crystal display device 100 described in Embodiment 1. Note that the video signal processing circuit 713 may also serve as the display control circuit 716 and the image processing circuit 724. With such a structure, the writing frequency of an image signal can be reduced; thus flicker due to rewriting is reduced, and eyestrain can be alleviated.

Next, FIG. 8A is an external view of a monitor (also referred to as a PC monitor) used for an electronic calculator (a personal computer) which is an electronic device. FIG. 8A illustrates a structure in which a housing 800 is mounted with a display module 801 manufactured using the display panel described in Embodiment 1 and is provided with a speaker 802, an external connection terminal 803, and the like. Note that in FIG. 8A, a window-type display portion 804 is illustrated so that a PC monitor can be easy to understand.

Note that although FIG. 8A illustrates so-called desktop PC monitor, a PC monitor for a laptop computer may be employed. Note that a display of the PC monitor displays a still image as well as a moving image. Here, the still image includes an image of a character, a diagram, a symbol, a photograph, a pattern, or a paintings; a combination any of them; or any of the images which are colored.

FIG. 8B is a block diagram of a main structure of a PC monitor. A PC monitor 810 illustrated in FIG. 8B includes a video signal processing circuit 813, an audio signal processing circuit 814, a display control circuit 816, a display panel 817, a gate line driver circuit 818, a source line driver circuit 819, a speaker 820, and an image processing circuit 824.

The video signal processing circuit 813 converts a video signal from an external arithmetic circuit 821 such as a CPU into a color signal corresponding to each color of red, green, and blue. The audio signal processing circuit 814 converts an audio signal from the external arithmetic circuit 821 such as a CPU into a signal which is output as the sound from the speaker 820. A signal output from the video signal processing circuit 813 and the audio signal processing circuit 814 varies depending on operation by an external operation means 822 such as a keyboard.

The display control circuit 816, the display panel 817, the gate line driver circuit 818, the source line driver circuit 819, and the image processing circuit 824 correspond to the display control circuit 113, the display panel 120, the gate line driver circuit 121A, the source line driver circuit 121B, and the image processing circuit 110 described in Embodiment 1 respectively. That is, a structure of a dotted line portion 823 corresponds to the liquid crystal display device 100 described in Embodiment 1. Note that the video signal processing circuit 813 may also serve as the display control circuit 816 and the image processing circuit 824. With such a structure, the writing frequency of an image signal can be reduced; thus flicker due to rewriting is reduced, and eyestrain can be alleviated.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)

In this embodiment, will be described an example of a structure of a backlight (also referred to as a backlight portion or a backlight unit) which can be used for the liquid crystal display device disclosed in this specification with reference to FIGS. 9A to 9C and FIGS. 10A to 10C.

FIG. 9A illustrates an example of a liquid crystal display device including a so-called edge-light type backlight portion 5201 and a display panel 5207. An edge-light type has a structure in which a light source is provided at an end of a backlight portion and light from the light source is emitted from the entire light-emitting surface.

The backlight portion 5201 includes a diffusion plate 5202 (also referred to as a diffusion sheet), a light guide plate 5203, a reflection plate 5204, a lamp reflector 5205, and a light source 5206. Note that the backlight portion 5201 may also include a luminance improvement film or the like.

The light source 5206 has a function of emitting light as necessary. For example, as the light source 5206, a cold cathode fluorescent lamp (CCFL), a light emitting diode, an EL element, or the like is used.

FIG. 9B illustrates a detailed structure of an edge-light type backlight portion. Note that description of the diffusion plate, the light guide plate, the reflection plate, and the like is omitted.

A backlight portion 5201 illustrated in FIG. 9B has a structure in which light-emitting diodes (LEDs) 5223 are used as light sources. For example, the light-emitting diodes (LEDs) 5223 which emit white light are provided at a predetermined interval. In addition, a lamp reflector 5222 is provided to efficiently reflect light from the light-emitting diodes (LEDs) 5223. Note that in the case where display is performed in combination with a field-sequential method, light-emitting diodes (LEDs) emitting colors of RGB may be used as light sources.

FIG. 9C illustrates an example of a liquid crystal display device including a so-called direct-below-type backlight portion and a liquid crystal panel. A direct-below type has a structure in which a light source is provided directly under a light-emitting surface and light from the light source is emitted from the entire light-emitting surface.

A backlight portion 5290 includes a diffusion plate 5291, a light-shielding portion 5292, a lamp reflector 5293, a light source 5294, and a liquid crystal panel 5295.

The light source 5294 has a function of emitting light as necessary. For example, for the light source 5294, a cold cathode fluorescent lamp, a light-emitting diode, an EL element which is a light-emitting element (e.g., an organic electroluminescence element), or the like is used.

Note that in the so-called direct-below-type backlight portion, the thickness of the backlight portion can be reduced with use of an EL element which is a light-emitting element as a light source. An example of a backlight portion using an EL element is illustrated in FIG. 10A.

A backlight portion 5290 illustrated in FIG. 10A includes an EL element 1025 provided over a substrate 1020. The EL element 1025 has a structure in which an EL layer 1003 including a light-emitting region is sandwiched between a pair of electrodes (an anode 1001 and a cathode 1002). Note that a substrate, a film, a protective film, or the like may be provided to cover the EL element 1025 so that the EL element 1025 may be sealed.

In this embodiment, since light from the EL layer 1003 is emitted to a display panel through the anode 1001, the anode 1001 may include a material which emits light such as an indium tin oxide (ITO). The cathode 1002 may include a material which reflects light such as an aluminum film. At least one of the anode 1001 and the cathode 1002 may have light-emitting properties.

Examples of element structures of the EL element 1025 in FIG. 10A are illustrated in FIGS. 10B and 10C.

The EL layer 1003 may include at least a light-emitting layer 1013, and may also have a structure in which the light-emitting layer 1013 and other functional layers are stacked. As the functional layer other than the light-emitting layer 1013, a layer containing a substance having a high hole-injection property, a substance having a high hole-transport property, a substance having a high electron-transport property, a substance having a high electron-injection property, a bipolar substance (a substance having high electron and hole transport properties), or the like can be used. Specifically, functional layers such as a hole-injection layer 1011, a hole-transport layer 1012, the light-emitting layer 1013, an electron-transport layer 1014, and an electron-injection layer 1015 can be used as appropriate in combination.

Next, materials that can be used for the above-described EL element 1025 are specifically described.

The anode 1001 is preferably made of a metal, an alloy, a conductive compound, a mixture thereof; or the like that has a high work function (specifically, a work function of 4.0 eV or higher). Specifically, it is possible to use, for example, conductive metal oxide such as indium oxide-tin oxide (ITO: indium tin oxide), indium oxide-tin oxide containing silicon or silicon oxide, indium oxide-zinc oxide (IZO: indium zinc oxide), or indium oxide containing tungsten oxide and zinc oxide.

Films of these conductive metal oxides are usually formed by sputtering; however, a sol-gel method or the like may also be used. For example, indium oxide-zinc oxide (IZO) can be formed by a sputtering method using indium oxide into which zinc oxide of 1 to 20 wt % is added, as a target. Indium oxide containing tungsten oxide and zinc oxide can be formed by a sputtering method using indium oxide into which tungsten oxide of 0.5 wt % to 5 wt % and zinc oxide of 0.1 wt % to 1 wt % are added, as a target.

Besides, as a material used for the anode 1001, it is also possible to use gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), titanium (Ti), nitride of a metal material (such as titanium nitride), molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, manganese oxide, titanium oxide, or the like.

The cathode 1002 can be made of a metal, an alloy, a conductive compound, a mixture thereof, or the like that has a low work function (specifically, a work function of 3.8 eV or lower). As a specific example of such a cathode material, an element belonging to Group 1 or 2 in the periodic table, i.e., an alkali metal such as lithium (Li) or cesium (Cs), or an alkaline earth metal such as magnesium (Mg), calcium (Ca), or strontium (Sr); an alloy containing any of these (such as MgAg or AlLi); a rare earth metal such as europium (Eu) or ytterbium (Yb); an alloy containing these; or the like can be used. Note that a film of an alkali metal, an alkaline earth metal, or an alloy thereof can be formed by a vacuum evaporation method. Further, an alkali metal or an alkaline earth metal can also be formed by a sputtering method. Further, a silver paste or the like can be formed by an inkjet method or the like.

In addition, the cathode 1002 can be formed by stacking a thin film of an alkali metal compound, an alkaline earth metal compound, or a rare earth metal compound (e.g., lithium fluoride (LiF), lithium oxide (LiO_(x)), cesium fluoride (CsF), calcium fluoride (CaF₂), or erbium fluoride (ErF₃)) and a film of a metal such as aluminum.

Next, specific examples of materials used for layers included in the EL layer 1003 are described below.

The hole-injection layer 1011 is a layer including a substance having a high hole-injection property. As the substance having a high hole-injection property, for example, molybdenum oxide, vanadium oxide, ruthenium oxide, tungsten oxide, manganese oxide, or the like can be used. Alternatively, the hole-injection layer 1011 can be formed using a phthalocyanine-based compound such as phthalocyanine (abbreviation: H₂Pc) or copper phthalocyanine (abbreviation: CuPc); an aromatic amine compound such as 4,4′-bis[N-(4-diphenylaminophenyl)-N-phenylamino]biphenyl (abbreviation: DPAB) or N,N′-bis[4-[bis(3-methylphenyl)amino]phenyl]-N,N′-diphenyl-[1,1′-biphenyl]-4,4′-diamine (abbreviation: DNTPD); a high molecule such as poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonic acid)(PEDOT/PSS); or the like. Further, the hole-injection layer 1011 can be formed using a tris(p-enamine-substituted-aminophenyl)amine compound, a 2,7-diamino-9-fluorenylidene compound, a tri(p-N-enamine-substituted-aminophenyl) benzene compound, a pyrene compound having one or two ethenyl groups having at least one aryl group, N,N′-di(biphenyl-4-yl)-N,N′-diphenylbiphenyl-4,4′-diamine, N,N,N′,N′-tetra(biphenyl-4-yl)biphenyl-4,4′-diamine, N,N,N′,N′-tetra(biphenyl-4-yl)-3,3′-diethylbiphenyl-4,4′-diamine, 2,2′-(methylenedi-4,1-phenylene)bis[4,5-bis(4-methoxyphenyl)-2H-1,2,3-triazole], 2,2′-(biphenyl-4,4′-diyl)bis(4,5-diphenyl-2H-1,2,3-triazole), 2,2′-(3,3′-dimethylbiphenyl-4,4′-diyl)bis(4,5-diphenyl-2H-1,2,3-triazole), bis[4-(4,5-diphenyl-2H-1,2,3-triazol-2-yl)phenyl](methyl)amine, or the like.

The hole-injection layer 1011 can also be formed of a hole-injection composite material including an organic compound and an inorganic compound (preferably, an inorganic compound having an electron-accepting property to an organic compound). Since electrons are transferred between the organic compound and the inorganic compound, the hole-injection composite material has a high carrier density, and thus has an excellent hole-injection property and a hole-transport property.

In the case where the hole-injection layer 1011 is made of a hole-injection composite material, the hole-injection layer 1011 can form an ohmic contact with the anode 1001; thus, the material of the anode 1001 can be selected regardless of the work function.

The inorganic compound used for the hole-injection composite material is preferably an oxide of a transition metal. In addition, an oxide of metals that belong to Group 4 to Group 8 in the periodic table can be given. Specifically, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, manganese oxide, and rhenium oxide are preferable since their electron-accepting properties are high. Among them, use of molybdenum oxide is especially preferable since it is stable in the air, has a low hygroscopic property, and is easily treated.

As the organic compound used for the hole-injection composite material, it is possible to use various compounds such as an aromatic amine compound, a carbazole derivative, an aromatic hydrocarbon, and a high molecular compound (oligomer, dendrimer, polymer, or the like). Note that the organic compound used for the hole-injection composite material is preferably an organic compound with a high hole-transport property. Specifically, a substance having a hole mobility greater than or equal to 10⁻⁶ cm²/Vs is preferably used. Note that substances other than the above described materials may also be used as long as the substances whose hole-transport property is higher than electron-transport property. The organic compounds that can be used for the hole-injection composite material are specifically described below.

As aromatic amine compounds, for example, there are N,N′-di(p-tolyl)-N,N′-diphenyl-p-phenylenediamine (abbreviation: DTDPPA), 4,4′-bis[N-(4-diphenylaminophenyl)-N-phenylamino]biphenyl (abbreviation: DPAB), N,N′-bis[4-[bis(3-methylphenyl)amino]phenyl]-N,N′-diphenyl-[1,1′-biphenyl]-4,4′-diamine (abbreviation: DNTPD), 1,3,5-tris[N-(4-diphenylaminophenyl)-N-phenylamino]benzene (abbreviation: DPA3B), and the like.

Specific examples of the carbazole derivative used for the hole-injection composite material include: 3-[N-(9-phenylcarbazol-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA1); 3,6-bis[N-(9-phenylcarbazol-3-yl)-N-phenylamino]-9-phenylcarbazole (abbreviation: PCzPCA2); 3-[N-(1-naphthyl)-N-(9-phenylcarbazol-3-yl)amino]-9-phenylcarbazole (abbreviation: PCzPCN1); and the like.

Moreover, 4,4′-di(N-carbazolyl)biphenyl (abbreviation: CBP); 1,3,5-tris[4-(N-carbazolyl)phenyl]benzene (abbreviation: TCPB); 9-[4-(N-carbazolyl)]phenyl-10-phenylanthracene (abbreviation: CzPA); 1,4-bis[4-(N-carbazolyl)phenyl]-2,3,5,6-tetraphenylbenzene; or the like can also be used.

Examples of the aromatic hydrocarbon used for the hole-injection composite material include: 2-tert-butyl-9,10-di(2-naphthyl)anthracene (abbreviation: t-BuDNA); 2-tert-butyl-9,10-di(1-naphthyl)anthracene; 9,10-bis(3,5-diphenylphenyl)anthracene (abbreviation: DPPA); 2-tert-butyl-9,10-bis(4-phenylphenyl)anthracene (abbreviation: t-BuDBA); 9,10-di(2-naphthyl)anthracene (abbreviation: DNA); 9,10-diphenylanthracene (abbreviation: DPAnth); 2-tert-butylanthracene (abbreviation: t-BuAnth); 9,10-bis(4-methyl-1-naphthyl)anthracene (abbreviation: DMNA); 2-tert-butyl-9,10-bis[2-(1-naphthyl)phenyl]anthracene; 9,10-bis[2-(1-naphthyl)phenyl]anthracene; 2,3,6,7-tetramethyl-9,10-di(1-naphthyl)anthracene; 2,3,6,7-tetramethyl-9,10-di(2-naphthyl)anthracene; 9,9′-bianthryl; 10,10′-diphenyl-9,9′-bianthryl; 10,10′-bis(2-phenylphenyl)-9,9′-bianthryl; 10,10′-bis[(2,3,4,5,6-pentaphenyl)phenyl]-9,9′-bianthryl; anthracene; tetracene; rubrene; perylene; 2,5,8,11-tetra(tert-butyl)perylene; and the like. Besides those, pentacene, coronene, or the like can also be used. In particular, the aromatic hydrocarbon having a hole mobility greater than or equal to 1×10⁻⁶ cm²/Vs and having 14 to 42 carbon atoms is particularly preferable.

Note that the aromatic hydrocarbon used for the hole-injection composite material may have a vinyl skeleton. As the aromatic hydrocarbon having a vinyl group, the following are given for example: 4,4′-bis(2,2-diphenylvinyl)biphenyl (abbreviation: DPVBi); 9,10-bis[4-(2,2-diphenylvinyl)phenyl]anthracene (abbreviation: DPVPA); and the like.

In addition, a high molecular compound such as poly(N-vinylcarbazole) (abbreviation: PVK) or poly(4-vinyltriphenylamine) (abbreviation: PVTPA) can also be used.

The hole-transport layer 1012 includes a substance having a high hole-transport property. As the substance having a high hole-transport property, for example, an aromatic amine compound (that is, a compound having a benzene ring-nitrogen bond) is preferable. As examples of the material which are widely used, the following can be given: 4,4′-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl; a derivative thereof such as 4,4′-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (hereinafter referred to as NPB); and a starburst aromatic amine compound such as 4,4′,4″-tris(N,N-diphenyl-amino)triphenylamine, 4,4′,4″-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine, and the like. The substances mentioned here are mainly ones that have a hole mobility higher than or equal to 10⁻⁶ cm²/Vs. Note that substances other than the above described materials may also be used as long as the substances have a higher hole-transport property than an electron-transport property. The hole-transport layer 1012 is not limited to a single layer, and may be a mixed layer of the aforementioned substances or a stacked layer of two or more layers each including the aforementioned substance.

Alternatively, a material with a hole-transport property may be added to a high molecular compound that is electrically inactive, such as PMMA.

Further alternatively, a high molecular compound such as poly(N-vinylcarbazole) (abbreviation: PVK), poly(4-vinyltriphenylamine) (abbreviation: PVTPA), poly[N-(4-{N′4-[4-(4-diphenylamino)phenyl]phenyl-N′-phenylamino}phenyl)methacrylamide] (abbreviation: PTPDMA), or poly[N,N′-bis(4-butylphenyl)-N,N′-bis(phenyl)benzidine (abbreviation: Poly-TPD) may be used, and further, the material with a hole-transport property may be added to the above high molecular compound, as appropriate. Further, the hole-transport layer 1012 can be formed using a tris(p-enamine-substituted-aminophenyl)amine compound, a 2,7-diamino-9-fluorenylidene compound, a tri(p-N-enamine-substituted-aminophenyl)benzene compound, a pyrene compound having one or two ethenyl groups having at least one aryl group, N,N′-di(biphenyl-4-yl)-N,N′-diphenylbiphenyl-4,4′-diamine, N,N,N′,N′-tetra(biphenyl-4-yl)biphenyl-4,4′-diamine, N,N,N′,N′-tetra(biphenyl-4-yl)-3,3′-diethylbiphenyl-4,4′-diamine, 2,2′-(methylenedi-4,1-phenylene)bis[4,5-bis(4-methoxyphenyl)-2H-1,2,3-triazole], 2,2′-(biphenyl-4,4′-diyl)bis(4,5-diphenyl-2H-1,2,3-triazole), 2,2′-(3,3′-dimethylbiphenyl-4,4′-diyl)bis(4,5-diphenyl-2H-1,2,3-triazole), bis[4-(4,5-diphenyl-2H-1,2,3-triazol-2-yl)phenyl](methyl)amine, or the like.

The light-emitting layer 1013 is a layer including a light-emitting substance and can be formed using a variety of materials. For example, as a light-emitting substance, a fluorescent compound which emits fluorescence or a phosphorescent compound which emits phosphorescence can be used. Organic compound materials which can be used for the light-emitting layer are described below. Note that materials which can be used for the EL element 1025 are not limited to these materials.

Blue to blue-green light emission can be obtained, for example, by using perylene, 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP), 9,10-diphenylanthracene, or the like as a guest material, and dispersing the guest material in a suitable host material. Alternatively, the blue to blue-green light emission can be obtained from a styrylarylene derivative such as 4,4′-bis(2,2-diphenylvinyl)biphenyl (abbreviation: DPVBi), or an anthracene derivative such as 9,10-di-2-naphthylanthracene (abbreviation: DNA) or 9,10-bis(2-naphthyl)-2-t-butylanthracene (abbreviation: t-BuDNA). Further, a polymer such as poly(9,9-dioctylfluorene) may be used. Further, as a guest material for blue light emission, a styrylamine derivative is preferable. Examples thereof include N,N′-bis[4-(9H-carbazol-9-yl)phenyl]-N,N′-diphenylstilbene-4,4′-diamine (abbreviation: YGA2S), N,N′-diphenyl-N,N′-bis(9-phenyl-9H-carbazol-3-yl)stilbene-4,4′-diamine (abbreviation: PCA2S), and the like. In particular, YGA2S is preferable because it has a peak at around 450 nm. Further, as a host material, an anthracene derivative is preferable; 9,10-bis(2-naphthyl)-2-t-butylanthracene (abbreviation: t-BuDNA) or 9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: CzPA) is suitable. In particular, CzPA is preferable because it is electrochemically stable.

Blue-green to green light emission can be obtained, for example, by using a coumarin dye such as coumarin 30 or coumarin 6, bis[2-(2,4-difluorophenyl)pyridinato]picolinatoiridium (abbreviation: FIrpic), bis(2-phenylpyridinato)acetylacetonatoiridium (abbreviation: Ir(ppy)₂(acac)), or the like as a guest material and dispersing the guest material in a suitable host material. Further, blue-green to green light emission can be obtained by dispersing perylene or TBP, which are mentioned above, in a suitable host material at a high concentration greater than or equal to 5 wt %. Further alternatively, the blue-green to green light emission can be obtained from a metal complex such as BAlq, Zn(BTZ)₂, or bis(2-methyl-8-quinolinolato)chlorogallium (Ga(mq)₂Cl). Further, a polymer such as poly(p-phenylenevinylene) may be used. An anthracene derivative is preferably used as a guest material of a blue-green to green light-emitting layer, as high light-emitting efficiency can be obtained. For example, when 9,10-bis{-4-[N-(4-diphenylamino)phenyl-N-phenyl]aminophenyl}-2-tert-butylanthracene (abbreviation: DPABPA) is used, highly efficient blue-green light emission can be obtained. In addition, an anthracene derivative in which an amino group has been substituted into the 2-position is preferable, as highly efficient green light emission can be obtained with such an anthracene derivative. In particular, N-(9,10-diphenyl-2-anthryl)-N,9-diphenyl-9H-carbazol-3-amine (abbreviation: 2PCAPA) is suitable, as it has a long life. As a host material for these materials, an anthracene derivative is preferable; CzPA, which is mentioned above, is preferable, as it is electrochemically stable. In the case where the EL element 1025 having two peaks in the blue to green wavelength range is manufactured by combining green light emission and blue light emission, an anthracene derivative having an electron-transport property, such as CzPA, is preferably used as a host material for a blue-light-emitting layer and an aromatic amine compound having a hole-transport property, such as NPB, is preferably used as a host material for a green-light-emitting layer, so that light emission can be obtained at the interface between the blue-light-emitting layer and the green-light-emitting layer. That is, in such a case, an aromatic amine compound like NPB is preferable as a host material of a green light-emitting material such as 2PCAPA.

Yellow to orange light emission can be obtained, for example, by using rubrene, 4-(dicyanomethylene)-2-[p-(dimethylamino)styryl]-6-methyl-4H-pyran (abbreviation: DCM1), 4-(dicyanomethylene)-2-methyl-6-(9-julolidyl)ethenyl-4H-pyran (abbreviation: DCM2), bis[2-(2-thienyl)pyridinato]acetylacetonatoiridium (abbreviation: Ir(thp)₂(acac)), bis(2-phenylquinolinato)acetylacetonatoiridium (abbreviation: Ir(pq)₂(acac)), or the like as a guest material and dispersing the guest material in a suitable host material. In particular, a tetracene derivative such as rubrene is preferable as a guest material because it is highly efficient and chemically stable. As a host material in this case, an aromatic amine compound such as NPB is preferable. Alternatively, a metal complex such as bis(8-quinolinolato)zinc(II) (abbreviation: Znq₂), bis[2-cinnamoyl-8-quinolinolato]zinc (abbreviation: Znsq₂), or the like can be used as a host material. Further alternatively, a polymer, such as poly(2,5-dialkoxy-1,4-phenylenevinylene) may be used.

Orange to red light emission can be obtained, for example, by using 4-(dicyanomethylene)-2,6-bis[p-(dimethylamino)styryl]-4H-pyran (abbreviation: BisDCM), 4-(dicyanomethylene)-2,6-bis[2-(julolidin-9-yl)ethenyl]-4H-pyran (abbreviation: BisDCJ), 4-(dicyanomethylene)-2-methyl-6-(9-julolidyl)ethenyl-4H-pyran (abbreviation: DCM2), bis[2-(2-thienyl)pyridinato]acetylacetonatoiridium (abbreviation: Ir(thp)₂(acac)), or the like as a guest material and dispersing the guest material in a suitable host material. Orange to red light emission can also be obtained by using a metal complex such as bis(8-quinolinolato)zinc(II) (abbreviation: Znq₂), bis[2-cinnamoyl-8-quinolinolato]zinc (abbreviation: Znsq₂), or the like. Further, a polymer such as poly(3-allylthiophene) may be used. As a guest material which exhibits red light emission, a 4H-pyran derivative such as 4-(dicyanomethylene)-2,6-bis[p-(dimethylamino)styryl]-4H-pyran (abbreviation: BisDCM), 4-(dicyanomethylene)-2,6-bis[2-(julolidin-9-yl)ethenyl]-4H-pyran (abbreviation: BisDCJ), 4-(dicyanomethylene)-2-methyl-6-(9-julolidyl)ethenyl-4H-pyran (abbreviation: DCM2), {2-isopropyl-6-[2-(2,3,6,7-tetrahydro-1,1,7,7-tetramethyl-1H,5H-benzo[ij]quinolizin-9-yl)ethenyl]-4H-pyran-4-ylidene}propanedinitrile (abbreviation: DCJTI), or {2,6-bis[2-(2,3,6,7-tetrahydro-8-methoxy-1,1,7,7-tetramethyl-1H,5H-benzo[ij]quinolizi n-9-yl)ethenyl]-4H-pyran-4-ylidene}propanedinitrile (abbreviation: BisDCJTM) is preferably used because of its high efficiency. In particular, DCJTI and BisDCJTM are preferable, as they have a light emission peak at around 620 nm.

Note that the light-emitting layer 1013 may have a structure in which the above light-emitting substance (a guest material) is dispersed in another substance (a host material). As the substance with which the substance having a high light-emitting property is dispersed, various kinds of materials can be used, and it is preferable to use a substance whose lowest unoccupied molecular orbital (LUMO) level is higher than that of a substance having a high light-emitting property and whose highest occupied molecular orbital (HOMO) level is lower than that of the substance having a high light-emitting property.

As the substance with which the substance having a light-emitting property is dispersed, specifically, a metal complex such as tris(8-quinolinolato)aluminum(III) (abbreviation: Alq), tris(4-methyl-8-quinolinolato)aluminum(III) (abbreviation: Almq₃), bis(10-hydroxybenzo[h]quinolinato)beryllium(II) (abbreviation: BeBq₂), bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum(III) (abbreviation: BAlq), bis(8-quinolinolato)zinc(II) (abbreviation: Znq₂), bis[2-(2-benzoxazolyl)phenolato]zinc(II) (abbreviation: ZnPBO), or bis[2-(2-benzothiazolyl)phenolato]zinc(II) (abbreviation: ZnBTZ); a heterocyclic compound such as 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazol-2-yl]benzene (abbreviation: OXD-7), 3-(4-biphenylyl)-4-phenyl-5-(4-tert-butylphenyl)-1,2,4-triazole (abbreviation: TAZ), 2,2′,2″-(1,3,5-benzenetriyl)tris(1-phenyl-1H-benzimidazole) (abbreviation: TPBI), bathophenanthroline (abbreviation: BPhen), or bathocuproine (abbreviation: BCP); a condensed aromatic compound such as 9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: CzPA), 3,6-diphenyl-9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazole (abbreviation: DPCzPA), 9,10-bis(3,5-diphenylphenyl)anthracene (abbreviation: DPPA), 9,10-di(2-naphthyl)anthracene (abbreviation: DNA), 2-tert-butyl-9,10-di(2-naphthyl)anthracene (abbreviation: t-BuDNA), 9,9′-bianthryl (abbreviation: BANT), 9,9′-(stilbene-3,3′-diyl)diphenanthrene (abbreviation: DPNS), 9,9′-(stilbene-4,4′-diyl)diphenanthrene (abbreviation: DPNS2), 3,3′,3″-(benzene-1,3,5-triyptripyrene (abbreviation: TPB3), 9,10-diphenylanthracene (abbreviation: DPAnth), or 6,12-dimethoxy-5,11-diphenylchrysene; an aromatic amine compound such as N,N-dipheyl-9-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazol-3-amine (abbreviation: CzAlPA), 4-(10-phenyl-9-anthryl)triphenylamine (abbreviation: DPhPA), N,9-diphenyl-N-[4-(10-phenyl-9-anthryl)phenyl]-9H-carbazol-3-amine (abbreviation: PCAPA), N,9-diphenyl-N-{4-[4-(10-phenyl-9-anthryl)phenyl]phenyl}-9H-carbazol-3-amine (abbreviation: PCAPBA), N-(9,10-diphenyl-2-anthryl)-N,9-diphenyl-9H-carbazol-3-amine (abbreviation: 2PCAPA), NPB (or α-NPD), TPD, DFLDPBi, or BSPB; or the like can be used.

As a substance with which the substance with a light-emitting property is dispersed, a plurality of kinds of substances can be used. For example, in order to suppress crystallization, a substance such as rubrene which suppresses crystallization, may be further added. In addition, NPB, Alq, or the like may be further added in order to efficiently transfer energy to the substance with a light-emitting property.

When a structure in which the substance having a light-emitting property is dispersed in another substance is employed, crystallization of the light-emitting layer 1013 can be suppressed. In addition, concentration quenching which results from high concentration of the substance having a light-emitting property can be suppressed.

The electron-transport layer 1014 is a layer including a substance having a high electron-transport property. As the substance having a high electron-transport property, for example, a layer containing a metal complex having a quinoline skeleton or a benzoquinoline skeleton, such as tris(8-quinolinolato)aluminum(III) (abbreviation: Alq), tris(4-methyl-8-quinolinolato)aluminum(III) (abbreviation: Almq₃), bis(10-hydroxybenzo[h]-quinolinato)beryllium (abbreviation: BeBq₂), or bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum (abbreviation: BAlq) can be used. In addition, a metal complex or the like including an oxazole-based or thiazole-based ligand, such as bis[2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: Zn(BOX)₂) or bis[2-(2-hydroxyphenyl)benzothiazolato]zinc(II) (abbreviation: Zn(BTZ)₂) can be used. Besides the metal complexes, 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazole-2-yl]benzene (abbreviation: OXD-7), 3-(4-biphenylyl)-4-phenyl-5-(4-tert-butylphenyl)-1,2,4-triazole (abbreviation: TAZ), bathophenanthroline (abbreviation: BPhen), bathocuproine (abbreviation: BCP), bis[3-(1H-benzimidazol-2-yl)fluoren-2-olato]zinc(II), bis[3-(1H-benzimidazol-2-yl)fluoren-2-olato]beryllium(II), bis[2-(1H-benzimidazol-2-yl)dibenzo[b,d]furan-3-olato](phenolato)aluminum(III), bis[2-(benzoxazol-2-yl)-7,8-methylenedioxydibenzo[b, d]furan-3-olato](2-naphtholato)aluminum(III), or the like can also be used. The substances mentioned here are mainly ones that have an electron mobility higher than or equal to 10⁻⁶ cm²/Vs. Note that the electron-transport layer 1014 may be formed of substances other than those described above as long as their electron-transport properties are higher than their hole-transport properties. The electron-transport layer 1014 is not limited to a single layer and may be a stacked layer which includes two or more layers each containing the aforementioned substance.

The electron-injection layer 1015 is a layer including a substance having a high electron-injection property. As the material having a high electron-injection property, the following can be given: an alkali metal or an alkaline earth metal such as lithium fluoride (LiF), cesium fluoride (CsF), and calcium fluoride (CaF₂), and a compound thereof. It is also possible to use an electron-injection composite material including an organic compound (preferably, an organic compound having an electron-transport property) and an inorganic compound (preferably, an alkali metal, an alkaline earth metal, a rare earth metal, or a compound of these metals). As the electron-injection composite material, for example, a layer made of Alq mixed with magnesium (Mg) may be used. Such a structure increases the efficiency in electron injection from the cathode 1002.

Note that in the case where the electron-injection layer 1015 is made of the aforementioned electron-injection composite material, a variety of conductive materials such as Al, Ag, ITO, or ITO containing silicon or silicon oxide can be used for the cathode 1002 regardless of the work function.

Such layers are stacked in appropriate combination, whereby the EL layer 1003 can be formed. The light-emitting layer 1013 may have a stacked-layer structure including two or more layers. The light-emitting layer 1013 has a stacked-layer structure including two or more layers and different light-emitting substances are used for respective light-emitting layers, so that a variety of emission colors can be obtained. In addition, a plurality of light-emitting substances of different colors are used as the light-emitting substance, whereby light emission having a broad spectrum or white light emission can also be obtained. In particular, for a backlight for which high luminance is required, a structure in which light-emitting layers are stacked is preferable.

Further, as a formation method of the EL layer 1003, a variety of methods (e.g., a dry process and a wet process) can be selected as appropriate depending on a material to be used. For example, a vacuum evaporation method, a sputtering method, an ink-jet method, a spin coating method, or the like can be used. Note that a different formation method may be employed for each layer.

The EL element 1025 described in this embodiment can be formed by any of a variety of methods regardless of whether it is a dry process (e.g., a vacuum evaporation method or a sputtering method) or a wet process (e.g., an ink-jet method or a spin coating method).

Note that the structure of the EL element 1025 described in this embodiment may be a structure in which a plurality of EL layers 1003 are stacked between a pair of electrodes as illustrated in FIG. 10C, that is, a stacked-layer element structure. Note that in the case of a structure in which n (n is a natural number of 2 or more) EL layers 1003 are stacked, an intermediate layer 1004 is provided between an m-th (m is a natural number greater than or equal to 1 and less than or equal to n−1) EL layer and an (m+1)-th EL layer.

The intermediate layer 1004 has a function of injecting electrons to one of the EL layers 1003 which is on the anode 1001 side and formed in contact with the intermediate layer 1004, and injecting holes to the other EL layer 1003 on the cathode 1002 side, when a voltage is applied to the anode 1001 and the cathode 1002.

The intermediate layer 1004 can be made by appropriately combining materials such as metal oxides as well as by using the aforementioned composite materials (the hole-injection composite material or the electron-injection composite material) of an organic compound and an inorganic compound. More preferably, the intermediate layer 1004 is made of a combination of the hole-injection composite material and other materials. Such materials used for the intermediate layer 1004 have an excellent carrier-injection property and carrier-transport property, whereby the EL element 1025 driven with low current and low voltage can be realized.

In a structure of the stacked-layer element, in the case where the EL layer has a two-layer stacked structure, white light can be extracted to the outside by allowing a first EL layer and a second EL layer to emit light of complementary colors. White light emission can also be obtained in a structure where each of the first EL layer and the second EL layer includes a plurality of light-emitting layers emitting light of complementary colors. As a complementary color relation, blue and yellow, blue-green and red, and the like can be given. A substance which emits light of blue, yellow, blue-green, or red light may be selected as appropriate from, for example, the light-emitting substances given above.

The following is an example of a structure where each of the first EL layer and the second EL layer includes a plurality of light-emitting layers emitting light of complementary colors. With this structure, white light emission can be obtained.

For example, the first EL layer includes a first light-emitting layer that emits light having an emission spectrum whose peak is in the blue to blue-green wavelength range, and a second light-emitting layer that emits light having and emission spectrum whose peak is in the yellow to orange wavelength range. The second EL layer includes a third light-emitting layer that emits light having an emission spectrum whose peak is in the blue-green to green wavelength range, and a fourth light-emitting layer that emits light having an emission spectrum whose peak is in the orange to red wavelength range.

In this case, light emission from the first EL layer is a combination of light emission from both the first light-emitting layer and the second light-emitting layer and thus exhibits a light emission spectrum having peaks both in the blue to blue-green wavelength range and in yellow to orange wavelength range. That is, the first EL layer emits light of 2-wavelength-type white color or 2-wavelength-type color that is similar to white.

In addition, light emission from the second EL layer is a combination of light emission from both the third light-emitting layer and the fourth light-emitting layer and thus exhibits a light emission spectrum having peaks both in the blue-green to green wavelength range and in the orange to red wavelength range. That is, the second EL layer emits light of 2-wavelength-type white color or 2-wavelength-type color that is similar to white, which is different from the first EL layer.

Consequently, by combining the light emission from the first EL layer and the light emission from the second EL layer, white light emission which covers the wavelength range of blue to blue-green, the wavelength range of blue-green to green, the wavelength range of yellow to orange, and the wavelength range of orange to red can be obtained.

Note that in the structure of the above-mentioned stacked layer element, by provision of intermediate layers between the stacked EL layers, the element can have long lifetime in a high-luminance region while the current density is kept low. In addition, the voltage drop due to resistance of the electrode material can be reduced, whereby uniform light emission in a large area is possible.

Note that the backlight portion described in FIGS. 9A to 9C and FIGS. 10A to 10C may have a structure in which luminance is adjusted. For example, luminance is adjusted in accordance with illuminance around the liquid crystal display device or luminance is adjusted in accordance with an image signal for display may be employed.

Note that color display is enabled by combination of color filters. Alternatively, other optical films (such as a polarizing film, a retardation film, and an anti-reflection film) can also be used in combination. Note that the color filter is not provided in the case where light-emitting diodes of RGB or the like are arranged in a backlight and a successive additive color mixing method (a field sequential method) in which color display is performed by time division is employed.

Note that this embodiment can be freely combined with the other embodiments.

(Embodiment 4)

In this embodiment, an example of a transistor that can be applied to a liquid crystal display device disclosed in this specification will be described. There is no particular limitation on a structure of the transistor that can be applied to the liquid crystal display device disclosed in this specification. For example, a staggered transistor, a planar transistor, or the like having a top-gate structure in which a gate electrode is provided above an oxide semiconductor layer with a gate insulating layer interposed or a bottom-gate structure in which a gate electrode is provided below an oxide semiconductor layer with a gate insulating layer interposed, can be used. The transistor may have a single gate structure including one channel formation region, a double gate structure including two channel formation regions, or a triple gate structure including three channel formation regions. Alternatively, the transistor may have a dual gate structure including two gate electrode layers provided over and below a channel region with a gate insulating layer interposed. FIGS. 11A to 11D illustrate examples of cross-sectional structures of transistors. Each of the transistors illustrated in FIGS. 11A to 11D includes an oxide semiconductor as a semiconductor. An advantage of using an oxide semiconductor is that field-effect mobility (the maximum value is higher than or equal to 5 cm²/Vsec, preferably in the range of 10 cm²/Vsec to 150 cm²/Vsec) can be obtained when a transistor is on, and low off current (lower than 1 aA/μm, preferably lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.) can be obtained when the transistor is off.

A transistor 410 illustrated in FIG. 11A is one of bottom-gate transistors and is also referred to as an inverted staggered transistor.

The transistor 410 includes, over a substrate 400 having an insulating surface, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405 a, and a drain electrode layer 405 b. An insulating film 407 is provided to cover the transistor 410 and be stacked over the oxide semiconductor layer 403. Further, a protective insulating layer 409 is formed over the insulating film 407.

A transistor 420 illustrated in FIG. 11B is one of bottom-gate transistors referred to as a channel-protective type (also referred to as a channel-stop type) and is also referred to as an inverted staggered transistor.

The transistor 420 includes, over the substrate 400 having an insulating surface, the gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, an insulating layer 427 functioning as a channel protective layer covering a channel formation region of the oxide semiconductor layer 403, the source electrode layer 405 a, and the drain electrode layer 405 b. Further, the protective insulating layer 409 is formed to cover the transistor 420.

A transistor 430 illustrated in FIG. 11C is a bottom-gate transistor and includes, over the substrate 400 having an insulating surface, the gate electrode layer 401, the gate insulating layer 402, the source electrode layer 405 a, the drain electrode layer 405 b, and the oxide semiconductor layer 403. The insulating film 407 is provided to cover the transistor 430 and to be in contact with the oxide semiconductor layer 403. Further, the protective insulating layer 409 is formed over the insulating film 407.

In the transistor 430, the gate insulating layer 402 is provided over and in contact with the substrate 400 and the gate electrode layer 401; the source electrode layer 405 a and the drain electrode layer 405 b are provided over and in contact with the gate insulating layer 402. The oxide semiconductor layer 403 is provided over the gate insulating layer 402, the source electrode layer 405 a, and the drain electrode layer 405 b.

A transistor 440 illustrated in FIG. 11D is one of top-gate transistors. The transistor 440 includes, over the substrate 400 having an insulating surface, an insulating layer 437, the oxide semiconductor layer 403, the source electrode layer 405 a, the drain electrode layer 405 b, the gate insulating layer 402, and the gate electrode layer 401. A wiring layer 436 a and a wiring layer 436 b are provided in contact with and electrically connected to the source electrode layer 405 a and the drain electrode layer 405 b respectively.

In this embodiment, the oxide semiconductor layer 403 is used as a semiconductor layer as described above. As an oxide semiconductor used for the oxide semiconductor layer 403, the following metal oxides can be used: a four-component metal oxide such as an In—Sn—Ga—Zn—O-based oxide semiconductor; a three-component metal oxide such as an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, and a Sn—Al—Zn—O-based oxide semiconductor; a two-component metal oxide such as an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, and an In—Mg—O-based oxide semiconductor; an In—O-based oxide semiconductor; a Sn—O-based oxide semiconductor; and a Zn—O-based oxide semiconductor. In addition, SiO₂ may be contained in the above oxide semiconductor. Here, for example, an In—Ga—Zn—O-based oxide semiconductor means an oxide film containing indium (In), gallium (Ga), and zinc (Zn), and there is no particular limitation on the stoichiometric proportion thereof. The In—Ga—Zn—O-based oxide semiconductor may contain an element other than In, Ga, and Zn.

As the oxide semiconductor layer 403, a thin film represented by a chemical formula of InMO₃(ZnO)_(m) (m>0, where m is not an integer) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example: M can be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like.

In each of the transistors 410, 420, 430, and 440 including the oxide semiconductor layer 403, the current value in an off state (off current value) can be reduced. Thus, the holding period of an electric signal such as an image signal can be extended and an interval between writing operations can be set longer in the state where power supply is on. Consequently, the frequency of refresh operation can be decreased, whereby power consumption can be effectively suppressed.

In addition, each of the transistors 410, 420, 430, and 440 including the oxide semiconductor layer 403 can operate at high speed because relatively high field-effect mobility can be obtained. Consequently, when the above transistors are used in a pixel portion of a liquid crystal display device, color separation can be suppressed and high-quality images can be obtained. In addition, since the above transistors can be provided in each of a driver circuit portion and a pixel portion over one substrate, the number of components of the liquid crystal display device can be reduced.

There is no limitation on a substrate that can be applied to the substrate 400 having an insulating surface; however, a glass substrate such as a glass substrate made of barium borosilicate glass or aluminosilicate glass is used.

In the bottom-gate transistors 410, 420, and 430, an insulating film serving as a base film may be provided between the substrate and the gate electrode layer. The base film has a function of preventing diffusion of an impurity element from the substrate, and can be formed to have a stacked-layer structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.

The gate electrode layer 401 can be formed to have a single-layer structure or a stacked-layer structure using any of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.

The gate insulating layer 402 can be formed with a single-layer structure or a stacked structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, and a hafnium oxide layer by a plasma CVD method, a sputtering method, or the like. For example, a silicon nitride layer (SiN_(y) (y>0)) having a thickness of 50 nm to 200 nm inclusive is formed as a first gate insulating layer by a plasma CVD method, and a silicon oxide layer (SiO_(x) (x>0)) having a thickness of 5 nm to 300 nm inclusive is formed as a second gate insulating layer over the first gate insulating layer, so that a gate insulating layer with a total thickness of 200 nm is formed.

As a conductive film used for the source electrode layer 405 a and the drain electrode layer 405 b, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W and a metal nitride film containing the above elements as its main component (a titanium nitride film, a molybdenum nitride film, and a tungsten nitride film) can be used. A metal film having a high melting point of Ti, Mo, W, or the like or a metal nitride film of these elements (a titanium nitride film, a molybdenum nitride film, and a tungsten nitride film) may be stacked on one of or both of a lower side or an upper side of a metal film of Al, Cu, or the like.

A conductive film functioning as the wiring layer 436 a and the wiring layer 436 b connected to the source electrode layer 405 a and the drain electrode layer 405 b can be formed using a material similar to that of the source electrode layer 405 a and the drain electrode layer 405 b.

The conductive film to be the source electrode layer 405 a and the drain electrode layer 405 b (including a wiring layer formed using the same layer as the source electrode layer 405 a and the drain electrode layer 405 b) may be formed using conductive metal oxide. As the conductive metal oxide, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), an alloy of indium oxide and tin oxide (In₂O₃—SnO₂, referred to as ITO), an alloy of indium oxide and zinc oxide (In₂O₃—ZnO), and such a metal oxide material containing silicon oxide can be used.

As the insulating films 407, 427, and 437, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like can be typically used.

For the protective insulating layer 409 provided over the oxide semiconductor layer, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film can be used.

Further, a planarization insulating film may be formed over the protective insulating layer 409 so that surface roughness due to the transistor is reduced. As the planarization insulating film, an organic material such as polyimide, acrylic, and benzocyclobutene can be used. Besides the above organic materials, a low-dielectric constant material (a low-k material) or the like can be used. Note that the planarization insulating film may be formed by stacking a plurality of insulating films formed of these materials.

An example of a pixel in a liquid crystal display device using such a transistor is illustrated in FIG. 18 and FIG. 19. FIG. 18 is a plan view of the pixel and FIG. 19 is a cross-sectional view taken along a line A-B shown in FIG. 18. Note that FIG. 18 illustrates a plan view of the substrate 400 over which the transistor 410 is formed, and FIG. 19 illustrates a structure in which a counter substrate 416 and a liquid crystal layer 414 are formed in addition to a structure of the substrate 400 over which a transistor 410 is formed. The following description will be given with reference to both FIG. 18 and FIG. 19.

The transistor 410 has the same structure as that of FIG. 11A, and includes the gate electrode layer 401, the gate insulating layer 402, and the oxide semiconductor layer 403. In a pixel, the gate electrode layer 401 is formed to extend in one direction. The oxide semiconductor layer 403 is provided to overlap with the gate electrode layer 401 with the gate insulating layer 402 interposed therebetween. The source electrode layer 405 a and the drain electrode layer 405 b are provided over the oxide semiconductor layer 403 (note that here, the terms “the source electrode layer 405 a” and “the drain electrode layer 405 b” are used just for convenience in order to distinguish electrodes in the transistor 410 between source and drain). The source electrode layer 405 a is extended in a direction to intersect with the gate electrode layer 401. A pixel electrode 411 is provided over the protective insulating layer 409, and the pixel electrode 411 is connected to the drain electrode layer 405 b through a contact hole 412. The pixel electrode 411 is formed from a transparent electrode material such as indium tin oxide, zinc oxide, or tin oxide.

A storage capacitor 419 may be provided as needed. When the storage capacitor 419 is provided, a capacitor wiring layer 417 formed from the same layer as the gate electrode layer 401 and a capacitor electrode layer 418 are included. Between the capacitor wiring layer 417 and the capacitor electrode layer 418, the gate insulating layer 402 is extended to function as a dielectric, so that the storage capacitor 419 is formed.

Slits are provided in the pixel electrode 411, whereby alignment of liquid crystal can be controlled. Such a structure is applied to a vertical alignment (VA) mode. The VA mode is a mode of controlling alignment of liquid crystal molecules of a liquid crystal panel. The VA mode is a mode in which liquid crystal molecules are aligned vertically to a panel surface when voltage is not applied. Note that other than the VA mode, a twisted nematic (TN) mode, a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a continuous pinwheel alignment (CPA) mode, a patterned vertical alignment (PVA) mode, or the like can be applied.

A counter electrode 415 is provided on the counter substrate 416 side. The liquid crystal layer 414 is provided between the substrate 400 and the counter substrate 416. An alignment film 413 is provided to be in contact with the liquid crystal layer 414. Alignment treatment for the alignment film 413 is made by an optical alignment method or a rubbing method. As a liquid crystal phase of the liquid crystal layer 414, a nematic phase, a smectic phase, a cholesteric phase, a blue phase, or the like can be used.

The following components constitutes one unit: the transistor 410 in which the oxide semiconductor layer 403 is provided to overlap with the gate electrode layer 401 with the gate insulating layer 402 interposed therebetween; the pixel electrode 411 which is connected to the source side or the drain side of the transistor 410 and drives liquid crystal; the counter electrode 415 provided to face the pixel electrode 411; and the liquid crystal layer 414 provided between the pixel electrode 411 and the counter electrode 415. A pixel can be constituted by the one or more of units, and the pixels are provided in matrix, whereby a display panel for displaying an image or the like can be formed.

In accordance with this embodiment, with a transistor including an oxide semiconductor layer having high field-effect mobility and low off current, a liquid crystal display device with less consumed power can be provided.

(Embodiment 5)

In this embodiment, examples of a transistor including an oxide semiconductor layer and a manufacturing method thereof will be described in detail below with reference to FIGS. 12A to 12E. The same portion as or a portion having a function similar to those in the above embodiment can be formed in a manner similar to that described in the above embodiment, and also the steps similar to those in the above embodiment can be performed in a manner similar to that described in the above embodiment, and repetitive description is omitted. In addition, detailed description of the same portions is not repeated.

FIGS. 12A to 12E illustrate an example of a cross-sectional structure of a transistor. A transistor 510 illustrated in FIGS. 12D and 12E is an inverted staggered thin film transistor having a bottom gate structure, which is similar to the transistor 410 illustrated in FIG. 11A.

Hereinafter, a manufacturing process of the transistor 510 over a substrate 505 is described with reference to FIGS. 12A to 12E.

First, a conductive film is formed over the substrate 505 having an insulating surface, and then, a gate electrode layer 511 is formed through a first photolithography step. Note that a resist mask may be formed by an inkjet method. Formation of the resist mask by an inkjet method needs no photomask; thus, manufacturing cost can be reduced.

As the substrate 505 having an insulating surface, a substrate similar to the substrate 400 described in Embodiment 4 can be used. In this embodiment, a glass substrate is used as the substrate 505.

An insulating film serving as a base film may be provided between the substrate 505 and the gate electrode layer 511. The base film has a function of preventing diffusion of an impurity element from the substrate 505, and can be formed with a single-layer structure or a stacked-layer structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.

The gate electrode layer 511 can be formed to have a single-layer structure or a stacked-layer structure using any of a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which includes any of these as a main component.

Next, a gate insulating layer 507 is formed over the gate electrode layer 511. The gate insulating layer 507 can be formed by a plasma CVD method, a sputtering method, or the like to have a single layer of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer or a stacked-layer structure thereof.

For the oxide semiconductor in this embodiment, an oxide semiconductor which is made to be an i-type semiconductor or a substantially i-type semiconductor by removing an impurity is used. Such a highly purified oxide semiconductor is highly sensitive to an interface state and interface charges; thus, an interface between the oxide semiconductor layer and the gate insulating layer is important. For that reason, the gate insulating layer that is to be in contact with a highly purified oxide semiconductor needs to have high quality.

For example, high-density plasma CVD using microwaves (e.g., with a frequency of 2.45 GHz) is preferably adopted because an insulating layer can be dense and have high withstand voltage and high quality. The highly purified oxide semiconductor and the high-quality gate insulating layer are in close contact with each other, whereby the interface state density can be reduced to obtain favorable interface characteristics.

Needless to say, another film formation method such as a sputtering method or a plasma CVD method can be employed as long as the method enables formation of a high-quality insulating layer as a gate insulating layer. Further, an insulating layer whose film quality and characteristics of the interface between the insulating layer and an oxide semiconductor are improved by heat treatment which is performed after formation of the insulating layer may be formed as a gate insulating layer. In any case, any insulating layer may be used as long as the insulating layer has characteristics of enabling reduction in interface state density of the interface between the insulating layer and an oxide semiconductor and formation of a favorable interface as well as having favorable film quality as a gate insulating layer.

In order to contain hydrogen, a hydroxyl group, and moisture in the gate insulating layer 507 and an oxide semiconductor film 530 as little as possible, it is preferable to perform pretreatment for formation of the oxide semiconductor film 530. As the pretreatment, the substrate 505 provided with the gate electrode layer 511 or a substrate 505 over which the gate electrode layer 511 and the gate insulating layer 507 are formed is preheated in a preheating chamber of a sputtering apparatus, whereby an impurity such as hydrogen or moisture adsorbed on the substrate 505 is removed and then, evacuation is performed. As an evacuation unit provided in the preheating chamber, a cryopump is preferable. Note that this preheating treatment can be omitted. Further, the above preheating may be performed in a similar manner, on the substrate 505 in a state where a source electrode layer 515 a and a drain electrode layer 515 b have been formed thereover but an insulating layer 516 has not been formed yet.

Next, over the gate insulating layer 507, the oxide semiconductor film 530 having a thickness greater than or equal to 2 nm and less than or equal to 200 nm, preferably greater than or equal to 5 nm and less than or equal to 30 nm is formed (see FIG. 12A).

Note that before the oxide semiconductor film 530 is formed by a sputtering method, powder substances (also referred to as particles or dust) which attach on a surface of the gate insulating layer 507 are preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering refers to a method in which, without applying a voltage to a target side, an RF power source is used for application of a voltage to a substrate side in an argon atmosphere to generate plasma in the vicinity of the substrate side to modify a surface. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used.

As an oxide semiconductor for the oxide semiconductor film 530, the oxide semiconductor described in Embodiment 4 can be used. Further, SiO₂ may be contained in the above oxide semiconductor. In this embodiment, the oxide semiconductor film 530 is deposited by a sputtering method with the use of an In—Ga—Zn—O-based oxide target. A cross-sectional view at this stage is illustrated in FIG. 12A. Alternatively, the oxide semiconductor film 530 can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen.

The target used for formation of the oxide semiconductor film 530 by a sputtering method is, for example, a metal oxide target containing In₂O₃, Ga₂O₃, and ZnO at a composition ratio of 1:1:1 [molar ratio], so that an In—Ga—Zn—O film is formed. Without limitation to the material and the component of the target, for example, a metal oxide target containing In₂O₃, Ga₂O₃, and ZnO at 1:1:2 [molar ratio] may be used.

The filling factor of the metal oxide target is greater than or equal to 90% and less than or equal to 100%, preferably greater than or equal to 95% and less than or equal to 99.9%. With use of the metal oxide target with high filling factor, a dense oxide semiconductor film can be formed.

It is preferable that a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or a hydride has been removed be used as a sputtering gas used for forming the oxide semiconductor film 530.

The substrate is held in a deposition chamber kept under reduced pressure, and the substrate temperature is set to 100° C. to 600° C. inclusive, preferably 200° C. to 400° C. inclusive. Formation of the oxide semiconductor film is conducted with heating the substrate, whereby the concentration of impurities included in the formed oxide semiconductor film can be reduced. In addition, damage by sputtering can be reduced. Then, a sputtering gas from which hydrogen and moisture are removed is introduced into the deposition chamber where remaining moisture is being removed, and the oxide semiconductor film 530 is deposited with use of the above target, over the substrate 505. In order to remove remaining moisture from the deposition chamber, an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump is preferably used. The evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with use of the cryopump, a hydrogen atom, a compound including a hydrogen atom, such as water (H₂O), (more preferably, also a compound including a carbon atom), and the like are removed, whereby the concentration of impurities in the oxide semiconductor film formed in the deposition chamber can be reduced.

As one example of the deposition condition, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the direct-current (DC) power source is 0.5 kW, and the atmosphere is an oxygen atmosphere (the proportion of the oxygen flow rate is 100%). Note that use of a pulse direct current (DC) power source is preferable because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform.

Then, through a second photolithography step, the oxide semiconductor film 530 is processed into an island-shaped oxide semiconductor layer. A resist mask for forming the island-shaped oxide semiconductor layer may be formed by an ink-jet method. Formation of the resist mask by an inkjet method needs no photomask; thus, manufacturing cost can be reduced.

In the case where a contact hole is formed in the gate insulating layer 507, a step of forming the contact hole can be performed at the same time as processing of the oxide semiconductor film 530.

Note that the etching of the oxide semiconductor film 530 may be dry etching, wet etching, or both dry etching and wet etching. As an etchant used for wet etching of the oxide semiconductor film 530, for example, a mixed solution of phosphoric acid, acetic acid, and nitric acid, such as ITO07N (produced by KANTO CHEMICAL CO., INC.) can be used.

Next, the oxide semiconductor layer is subjected to first heat treatment. By this first heat treatment, the oxide semiconductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then, the oxide semiconductor layer is not exposed to the air so that entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, an oxide semiconductor layer 531 is obtained (see FIG. 12B).

Further, a heat treatment apparatus used in this step is not limited to an electric furnace, and a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be alternatively used. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. As the high temperature gas, an inert gas which does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas like argon, is used.

For example, as the first heat treatment, GRTA may be performed as follows: the substrate is transferred and put into an inert gas heated to a high temperature as high as 650° C. to 700° C., heated for several minutes, and taken out from the inert gas heated to the high temperature.

Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not contained in the atmosphere of nitrogen or a rare gas such as helium, neon, or argon. The purity of nitrogen or the rare gas such as helium, neon, or argon which is introduced into the heat treatment apparatus is preferably set to be 6N (99.9999%) or higher, far preferably 7N (99.99999%) or higher (that is, the impurity concentration is preferably 1 ppm or lower, far preferably 0.1 ppm or lower).

After the oxide semiconductor layer is heated by the first heat treatment, a high-purity oxygen gas, a high-purity N₂O gas, or ultra-dry air (having a dew point of −40° C. or lower, preferably −60° C. or lower) may be introduced into the same furnace. It is preferable that water, hydrogen, or the like be not contained in the oxygen gas or the N₂O gas. Alternatively, the purity of an oxygen gas or an N₂O gas which is introduced into the heat treatment apparatus is preferably 6N or more, further preferably 7N or more (i.e., the impurity concentration of the oxygen gas or the N₂O gas is 1 ppm or lower, preferably 0.1 ppm or lower). Although oxygen which is a main component included in the oxide semiconductor has been reduced through the elimination of impurities by performance of dehydration treatment or dehydrogenation treatment, oxygen is supplied by the effect of introduction of the oxygen gas or the N₂O gas in the above manner, so that the oxide semiconductor layer is highly purified and made to be an electrically i-type (intrinsic) semiconductor.

Alternatively, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 530 which has not yet been processed into the island-shaped oxide semiconductor layer. In that case, the substrate is taken out from the heat apparatus after the first heat treatment, and then a photolithography step is performed.

Note that other than the above timing, the first heat treatment may be performed at any of the following timings as long as it is after the oxide semiconductor film is formed. For example, the timing may be after a source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer or after an insulating layer is formed over the source electrode layer and the drain electrode layer.

Further, in the case where a contact hole is formed in the gate insulating layer 507, the formation of the contact hole may be performed before or after the first heat treatment is performed on the oxide semiconductor film 530.

Alternatively, an oxide semiconductor layer may be formed through two deposition steps and two heat treatment steps. The thus formed oxide semiconductor layer has a thick crystalline region (non-single-crystal region), that is, a crystalline region the c-axis of which is aligned in a direction perpendicular to a surface of the layer, even when a base component includes any of an oxide, a nitride, a metal, or the like. For example, a first oxide semiconductor film with a thickness greater than or equal to 3 nm and less than or equal to 15 nm is deposited, and first heat treatment is performed in a nitrogen, oxygen, rare gas, or dry air atmosphere at 450° C. to 850° C. inclusive, preferably 550° C. to 750° C. inclusive, so that the first oxide semiconductor film has a crystalline region (including a plate-like crystal) in a region including its surface. Then, a second oxide semiconductor film which has a larger thickness than the first oxide semiconductor film is formed, and second heat treatment is performed at 450° C. to 850° C. inclusive, preferably 600° C. to 700° C. inclusive, so that crystal growth proceeds upward with use of the first oxide semiconductor film as a seed of the crystal growth and the whole second oxide semiconductor film is crystallized. In such a manner, the oxide semiconductor layer having a thick crystalline region may be obtained.

Next, a conductive film to be the source and drain electrode layers (including a wiring formed in the same layer as the source and drain electrode layers) is formed over the gate insulating layer 507 and the oxide semiconductor layer 531. The conductive film to be the source and drain electrode layers can be formed using the material which is used for the source electrode layer 405 a and the drain electrode layer 405 b described in Embodiment 4.

By performance of a third photolithography step, a resist mask is formed over the conductive film, and selective etching is performed, so that the source electrode layer 515 a and the drain electrode layer 515 b are formed. Then, the resist mask is removed (see FIG. 12C).

Light exposure at the time of the formation of the resist mask in the third photolithography step may be performed using ultraviolet light, KrF laser light, or ArF laser light. A channel length L of the transistor formed later is determined by the distance between the lower edge portion of the source electrode layer and the lower edge portion of the drain electrode layer which are next to each other over the oxide semiconductor layer 531. In the case where a channel length L is less than 25 nm, light exposure for formation of the resist mask in the third photolithography step may be performed using extreme ultraviolet light having an extremely short wavelength of several nanometers to several tens of nanometers. In the light exposure by extreme ultraviolet light, the resolution is high and the focal depth is large. For these reasons, the channel length L of the transistor to be formed later can be in the range of 10 nm to 1000 nm inclusive, and the circuit can operate at higher speed.

In order to reduce the number of photomasks used in a photolithography step and reduce the number of steps, an etching step may be performed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted to have a plurality of intensities. A resist mask formed with use of a multi-tone mask has a plurality of thicknesses and further can be changed in shape by etching; therefore, the resist mask can be used in a plurality of etching steps for processing into different patterns. Therefore, a resist mask corresponding to at least two or more kinds of different patterns can be formed with one multi-tone mask. Thus, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can be also reduced, whereby simplification of a process can be realized.

Note that when the conductive film is etched, the optimum etching condition is desirably made so that the oxide semiconductor layer 531 can be prevented to be etched together with the conductive film and divided. However, it is difficult to attain such a condition that only the conductive film is etched and the oxide semiconductor layer 531 is not etched at all. In etching of the conductive film, the oxide semiconductor layer 531 is partly etched in some cases, whereby the oxide semiconductor layer having a groove portion (a depressed portion) is formed.

In this embodiment, since a titanium (Ti) film is used as the conductive film and the In—Ga—Zn—O-based oxide semiconductor is used for the oxide semiconductor layer 531, an ammonium hydrogen peroxide mixture (31 wt. % hydrogen peroxide water: 28 wt. % ammonia water: water=5:2:2) is used as an etchant of the Ti film.

Next, by plasma treatment using a gas such as N₂O, N₂, or Ar, water or the like adsorbed to a surface of an exposed portion of the oxide semiconductor layer may be removed. In the case where the plasma treatment is performed, the insulating layer 516 which serves as a protective insulating film in contact with part of the oxide semiconductor layer is formed without exposure to the air.

The insulating layer 516 can be formed to a thickness of at least 1 nm by a method by which an impurity such as water or hydrogen does not enter the insulating layer 516, such as a sputtering method as appropriate. When hydrogen is contained in the insulating layer 516, the hydrogen enters the oxide semiconductor layer or extracts oxygen from the oxide semiconductor layer, which causes a reduction in resistance of a back channel of the oxide semiconductor layer (i.e., makes an n-type back channel), so that a parasitic channel might be formed. Therefore, it is important for the insulating layer 516 that hydrogen is not used in a formation method in order to contain hydrogen as little as possible.

In this embodiment, a silicon oxide film is formed to a thickness of 200 nm as the insulating layer 516 by a sputtering method. The substrate temperature in film formation may be higher than or equal to room temperature and lower than or equal to 300° C. and in this embodiment, is 100° C. The silicon oxide film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen. As a target, a silicon oxide target or a silicon target may be used. For example, the silicon oxide film can be formed using a silicon target by a sputtering method in an atmosphere containing oxygen. As the insulating layer 516 which is formed in contact with the oxide semiconductor layer, an inorganic insulating film which does not include an impurity such as moisture, a hydrogen ion, or OH⁻ and blocks the entry of the impurity from the outside is used. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

As in the case of formation of the oxide semiconductor film 530, an adsorption-type vacuum pump such as a cryopump is preferably used in order to remove remaining moisture in a deposition chamber of the insulating layer 516. When the insulating layer 516 is deposited in the deposition chamber which is evacuated with use of a cryopump, the concentration of an impurity contained in the insulating layer 516 can be reduced. Alternatively, the evacuation unit used for removal of the remaining moisture in the deposition chamber may be a turbo pump provided with a cold trap.

It is preferable that a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or a hydride have been removed be used as a sputtering gas used for forming the insulating layer 516.

Next, second heat treatment is performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably at from 200° C. to 400° C. inclusive, e.g. 250° C. to 350° C. inclusive). For example, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. The second heat treatment is performed in such a condition that part (a channel formation region) of the oxide semiconductor layer is in contact with the insulating layer 516.

As described above, an impurity such as hydrogen, moisture, a hydroxyl group, or a hydride (also referred to as a hydrogen compound) is intentionally removed from the oxide semiconductor layer by subjecting the oxide semiconductor layer to the first heat treatment, and then oxygen which is one of main components of the oxide semiconductor can be supplied because oxygen has been reduced in the step of removing impurities. Through the above steps, the oxide semiconductor layer is highly purified and is made to be an electrically i-type (intrinsic) semiconductor.

Through the above process, the transistor 510 is formed (see FIG. 12D).

When a silicon oxide layer having a lot of defects is used as the insulating layer 516, an impurity such as hydrogen, moisture, a hydroxyl group, or a hydride contained in the oxide semiconductor layer can be diffused by the heat treatment which is performed after the formation of the silicon oxide layer, so that impurities in the oxide semiconductor layer can be further reduced.

A protective insulating layer 506 may be formed over the insulating layer 516. For example, a silicon nitride film is formed by an RF sputtering method. Since an RF sputtering method has high productivity, it is a preferable method used for formation of the protective insulating layer. As the protective insulating layer, an inorganic insulating film which does not include an impurity such as moisture and blocks entry of the impurity from the outside, e.g., a silicon nitride film, an aluminum nitride film, or the like is used. In this embodiment, the protective insulating layer 506 is formed using a silicon nitride film (see FIG. 12E).

In this embodiment, as the protective insulating layer 506, a silicon nitride film is formed by heating the substrate 505 over which the steps up to and including the formation step of the insulating layer 516 have been done, to a temperature of 100° C. to 400° C., introducing a sputtering gas including high-purity nitrogen from which hydrogen and moisture are removed, and using a silicon semiconductor target. In that case also, it is preferable that remaining moisture be removed from a deposition chamber in the formation of the protective insulating layer 506 as in the case of the insulating layer 516.

After the formation of the protective insulating layer, heat treatment may be further performed at a temperature from 100° C. to 200° C. inclusive in the air for one hour to 30 hours inclusive. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to room temperature.

A transistor including a highly purified oxide semiconductor layer which is manufactured in accordance with this embodiment as described achieves high filed-effect mobility and thus can operate at high speed. When the transistor including a highly purified oxide semiconductor layer is used in a pixel portion in the liquid crystal display device, color separation can be suppressed and a high-quality image can be provided. In addition, by using the transistors including a highly purified oxide semiconductor layer, a driver circuit portion and a pixel portion are formed over one substrate; thus, the number of components of the liquid crystal display device can be reduced.

Measurement results of the field-effect mobility of a transistor including a highly purified oxide semiconductor are described.

In accordance with the above manufacturing method of this embodiment, a transistor (L/W=10 μm/50 μm) including a highly purified oxide semiconductor (an In—Ga—Zn—O-based oxide semiconductor film with a thickness of 50 nm) was manufactured, and a change in characteristics of source-drain current (hereinafter, referred to as drain current or I_(d)) was measured under conditions that the substrate temperature was set to room temperature, source-drain voltage (hereinafter, referred to as drain voltage or V_(d)) was set to 10 V, and source-gate voltage (hereinafter, referred to as gate voltage or V_(g)) was changed from −30 V to +30 V. That is, V_(g)-I_(d) characteristics were measured. Note that in FIG. 13, the range of V_(g) is from −5 V to +30 V. From FIG. 13, the maximum value of field-effect mobility of the transistor including a highly purified oxide semiconductor layer can be confirmed to be 10.7 cm²Nsec.

Further, the transistor including a highly purified oxide semiconductor can achieve further reduction in the current value in an off state (off-current value). Therefore, the holding period of an electric signal of an image signal or the like can be extended and an interval between writing operations can be set longer. Thus, the frequency of refresh operation can be reduced, whereby a decrease in consumed power can be more effectively improved.

In addition, measurement results of the off current of a transistor including a highly purified oxide semiconductor are described.

In accordance with the above manufacturing method of this embodiment, a transistor including a highly purified oxide semiconductor was manufactured. First, a transistor with a sufficiently large channel width W of 1 cm was prepared in consideration of the very small off current of the transistor including a highly purified oxide semiconductor, and the off current was measured. FIG. 14 shows the measurement results of the off current of the transistor with a channel width W of 1 cm. In FIG. 14, the horizontal axis indicates the gate voltage V_(g) and the vertical axis indicates the drain current I_(d). In the case where the drain voltage V_(d) is +1 V or +10 V, the off current of the transistor with the gate voltage V_(g) within the range of −5 V to −20 V was found to be smaller than or equal to 1×10⁻¹³ A which is the detection limit. Moreover, it was found that the off current of the transistor (per unit channel width (1 μm)) was smaller than or equal to 10 aA/μm (1×10⁻¹⁷ A/μm).

Next, more accurate measurement results of the off current of the transistor including a highly purified oxide semiconductor are described. As described above, the off current of the transistor including a highly purified oxide semiconductor was found to be smaller than or equal to 1×10⁻¹³ A which is the detection limit of measurement equipment. Thus, more accurate off current (the value smaller than or equal to the detection limit of measurement equipment in the above measurement) was measured with use of an element for characteristic evaluation. The results thereof will be described.

The element for characteristic evaluation used in the current measurement is described below.

As the element for characteristic evaluation, three measurement systems which are connected in parallel are used. Each measurement system includes a capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first to fourth transistors were manufactured in accordance with this embodiment, and each transistor had the same structure as the transistor 510 illustrated in FIG. 12D.

In each measurement system, one of a source terminal and a drain terminal of the first transistor, one of terminals of the capacitor, and one of a source terminal and a drain terminal of the second transistor are connected to a power supply (for supplying V2). The other of the source terminal and the drain terminal of the first transistor, one of a source terminal and a drain terminal of the third transistor, the other of the terminals of the capacitor, and a gate terminal of the second transistor are connected to one another. The other of a source terminal and a drain terminal of the third transistor, one of a source terminal and a drain terminal of the fourth transistor, and a gate terminal of the fourth transistor are connected to a power supply (for supplying V1). The other of the source terminal and the drain terminal of the second transistor, the other of the source terminal and the drain terminal of the fourth transistor are connected to an output terminal.

A potential V_(ext) _(—) _(b2) for controlling whether to turn on or off the first transistor is supplied to the gate terminal of the first transistor. A potential V_(ext) _(—) _(b1) for controlling whether to turn on or off the third transistor is supplied to the gate terminal of the third transistor. A potential V_(out) is output from the output terminal.

Then, the measurement of the off current with use of the above measurement systems is described.

First, a potential difference is given between the source terminal and the drain terminal of the first transistor and between the source terminal and the drain terminal of the third transistor in an initialization period. After the initialization is completed, the potential of the gate terminal of the second transistor varies over time due to the off current of the first and third transistors. Accordingly, potential of the output potential V_(out) of the output terminal varies over time. Then, the off current can be calculated with the thus obtained output potential V_(out).

Each of the first to fourth transistors is a transistor including a highly purified oxide semiconductor with a channel length L of 10 μm and a channel width W of 50 μm. In the three measurement systems arranged in parallel, the capacitance of the capacitor in the first measurement system was 100 fF, the capacitance of the capacitor in the second measurement system was 1 pF, and the capacitance of the capacitor in the third measurement system was 3 pF.

V1 and V2 were appropriately set to be 5 V or 0 V in order to provide the potential difference between the source terminal and the drain terminal of the first transistor and between the source terminal and the drain terminal of the third transistor. The measurement was carried out every 10 to 300 seconds, and the potential V_(out) was measured for 100 msec in every measurement. The measurement was conducted until 30000 seconds have passed after the initialization.

FIG. 15 shows the off current which was calculated in the above current measurement. FIG. 15 further shows the relationship between source-drain voltage V and off current I. According to FIG. 15, the off current was about 40 zA/μm at the source-drain voltage of 4 V. In a similar way, the off current was less than or equal to 10 zA/μm at the source-drain voltage of 3.1 V. Note that 1 zA represents 10⁻²¹ A.

According to this embodiment, it was confirmed that the off current can be sufficiently small in a transistor including a highly purified oxide semiconductor.

(Embodiment 6)

A liquid crystal display device disclosed in this specification can be applied to a variety of electronic devices (including game machines). Examples of electronic devices are a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone handset (also referred to as a mobile phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like. Examples of electronic devices each including the liquid crystal display device described in the above embodiment are described.

FIG. 16A illustrates an electronic book reader (also referred to as an e-book reader), which includes a housing 9630, a display portion 9631, operation keys 9632, a solar cell 9633, and a charge and discharge control circuit 9634. The e-book reader illustrated in FIG. 16A has a function of displaying various kinds of information (e.g., a still image, a moving image, and a text image) on the display portion, a function of displaying a calendar, a date, the time, or the like on the display portion, a function of operating or editing the information displayed on the display portion, a function of controlling processing by various kinds of software (programs), and the like. Note that, in FIG. 16A, the charge and discharge control circuit 9634 has a battery 9635 and a DCDC converter (hereinafter, abbreviated as a converter) 9636 as an example. When the liquid crystal display device described in any of Embodiments 1 to 5 is applied to the display portion 9631, an e-book reader which consumes less power can be provided.

In the case of using a transflective or reflective liquid crystal display device as the display portion 9631 in the structure illustrated in FIG. 16A, the e-book reader is assumed to be used in a comparatively bright environment. In that case, power generation by the solar cell 9633 and charge by the battery 9635 can be effectively performed, which is preferable. Since the solar cell 9633 can be provided on a space (a surface or a rear surface) of the housing 9630 as appropriate, the battery 9635 can be efficiently charged, which is preferable. Note that using a lithium ion battery as the battery 9635 has the advantage of downsizing can be achieved, for example.

A configuration and operation of the charge and discharge control circuit 9634 illustrated in FIG. 16A is described with reference to a block diagram of FIG. 16B. FIG. 16B shows the solar cell 9633, the battery 9635, the converter 9636, a converter 9637, switches SW1 to SW3, and the display portion 9631. The charge and discharge control circuit 9634 includes the battery 9635, the converter 9636, the converter 9637, and the switches SW1 to SW3.

First, an example of operation of when the solar cell 9633 generates power by using external light is described. The power generated by the solar cell is raised or lowered by the converter 9636 to be the voltage for charging the battery 9635. When the power from the solar cell 9633 is used for operation of the display portion 9631, the switch SW1 is turned on and the power is raised or lowered by the converter 9637 to be the voltage needed for the display portion 9631. When display is not performed on the display portion 9631, the switch SW1 may be turned off and the switch SW2 may be turned on, whereby the battery 9635 is charged.

Next, an example of operation of when the solar cell 9633 does not generate power by using external light is described. The power stored in the battery 9635 is raised or lowered by the converter 9637 when the switch SW3 is turned on. Then, the power from the battery 9635 is used for operation of the display portion 9631.

Note that the solar cell 9633 is described as an example of a charging unit here; however, charging the battery 9635 may be performed by another unit. Alternatively, a combination of another charging unit may be used.

FIG. 17 illustrates a laptop personal computer, which includes a main body 3001, a housing 3002, a display portion 3003, a keyboard 3004, and the like. When the liquid crystal display device described in any of Embodiments 1 to 5 is applied to the display portion 3003, power consumption in a laptop personal computer can be small.

This embodiment can be implemented in appropriate combination with the configurations described in the other embodiments.

This application is based on Japanese Patent Application serial no. 2010-012664 filed with Japan Patent Office on Jan. 24, 2010, the entire contents of which are hereby incorporated by reference.

Explanation of Reference

100: liquid crystal display device, 110: image processing circuit, 111: memory circuit, 111b: frame memory, 112: comparison circuit, 113: display control circuit, 115: selection circuit, 116: power supply, 120: display panel, 121: driver circuit portion, 121A: gate line driver circuit, 121B: source line driver circuit, 122: pixel portion, 123: pixel, 124: gate line, 125: source line, 126: terminal portion, 126A: terminal, 126B: terminal, 127: switching element, 128: common electrode, 130: backlight portion, 131: backlight control circuit, 132: backlight, 210: capacitor, 213: pixel, 214: transistor, 215: liquid crystal element, 225: hole-injection layer, 400: substrate, 401: gate electrode layer, 402: gate insulating layer, 403: oxide semiconductor layer, 405a: source electrode layer, 405b: drain electrode layer, 407: insulating film, 409: protective insulating layer, 410: transistor, 411: pixel electrode, 412: contact hole, 413: alignment film, 414: liquid crystal layer, 415: counter electrode, 416: counter substrate, 417: capacitor wiring layer, 418: capacitor electrode layer, 419: storage capacitor, 420: transistor, 427: insulating layer, 430: transistor, 436a: wiring layer, 436b: wiring layer, 437: insulating layer, 440: transistor, 505: substrate, 506: protective insulating layer, 507: gate insulating layer, 510: transistor, 511: gate electrode layer, 515a: source electrode layer, 515b: drain electrode layer, 516: insulating layer, 530: oxide semiconductor film, 531: oxide semiconductor layer, 601: period, 602: period, 603: period, 604: period, 700: housing, 701: display module, 702: speaker, 703: operation key, 704: external connection terminal, 705: illuminance sensor, 710: television receiver, 711: tuner, 712: digital demodulation circuit, 713: video signal processing circuit, 714: audio signal processing circuit, 715: display adjustment circuit, 716: display control circuit, 717: display panel, 718: gate line driver circuit, 719: source line driver circuit, 720: speaker, 721: antenna, 722: external input portion, 723: dotted line portion, 724: image processing circuit, 800: housing, 801: display module, 802: speaker, 803: external connection tenninal, 804: window-type display portion, 810: PC monitor, 813: video signal processing circuit, 814: audio signal processing circuit, 815: audio signal processing circuit, 816: display control circuit, 817: display panel, 818: gate line driver circuit, 819: source line driver circuit, 820: speaker, 821: external arithmetic circuit, 822: external operation means, 823: dotted line portion, 824: image processing circuit, 1001: anode, 1002: cathode, 1003: EL layer, 1004: intermediate layer, 1011: hole-injection layer, 1012: hole-transport layer, 1013: light-emitting layer, 1014: electron-transport layer, 1015: electron-injection layer, 1020: substrate, 1025: EL element, 1401: period, 1402: period, 1403: period, 1404: period, 3001: main body, 3002: housing, 3003: display portion, 3004: keyboard, 5201: backlight portion, 5202: diffusion plate, 5203: light guide plate, 5204: reflection plate, 5205: lamp reflector, 5206: light source, 5207: display panel, 5222: lamp reflector, 5223: light-emitting diode (LED), 5290: backlight portion, 5291: diffusion plate, 5292: light-shielding portion, 5293: lamp reflector, 5294: light source, 5295: liquid crystal panel, 9630: housing, 9631: display portion, 9632: operation key, 9633: solar cell, 9634: charge and discharge control circuit, 9635: battery, 9636: converter, 9637: converter 

The invention claimed is:
 1. A display device provided with a display panel comprising: a pixel portion comprising a pixel, wherein the pixel comprises a liquid crystal display element and a first transistor including an oxide semiconductor layer; a driver circuit portion configured to drive the pixel portion and display an image on a screen; and a switching element comprising a second transistor including the oxide semiconductor layer, wherein the oxide semiconductor layer comprises a crystal, wherein a c-axis of the crystal is aligned in a direction perpendicular to a surface of the oxide semiconductor layer, wherein the first transistor and the second transistor are connected to each other with the liquid crystal display element, wherein the driver circuit portion has a function to write a first image signal and a second image signal to the pixel successively so as to display an image on the screen, and a function to stop a writing operation of the second image signal and turn the first transistor off so as to maintain one image written to the screen when a difference is not detected between the first image signal and the second image signal, and wherein an off current of each of the first transistor and the second transistor is lower than 10 zA/μ m at room temperature and lower than 100 zA μ m at 85 ° C.
 2. The display device according to claim 1, wherein an interval between the first image signal and the second image signal written to the pixel is longer than one second when a difference is not detected between the first image signal and the second image signal.
 3. The display device according to claim 1, further comprising a lighting unit, wherein a light source of the lighting unit is a light-emitting diode or an organic electroluminescence element.
 4. The display device according to claim 1, wherein the driver circuit portion comprises a gate line driver circuit configured to transmit a signal to a gate electrode of the first transistor, and wherein the gate line driver circuit is formed over a substrate over which the pixel portion is formed.
 5. The display device according to claim 1, wherein the driver circuit portion comprises a signal line driver circuit configured to transmit a signal to a source electrode or a drain electrode of the first transistor, and wherein the signal line driver circuit is formed over a substrate over which the pixel portion is formed.
 6. The display device according to claim 1, wherein the oxide semiconductor layer is an intrinsic semiconductor or a substantially intrinsic semiconductor, and wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer.
 7. The display device according to claim 1, further comprising a storage capacitor connected to a pixel electrode, and wherein the storage capacitor is provided in parallel to a liquid crystal layer of the liquid crystal display element.
 8. The display device according to claim 1, wherein potentials of a pixel electrode and a common electrode are set in a floating state when a difference is not detected between the first image signal and the second image signal.
 9. The display device according to claim 1, wherein a thin film represented by a chemical formula of InMO₃(ZnO)_(m)(m>0, where m is not an integer) is used as the oxide semiconductor layer, and wherein M represents one or more metal elements selected from Ga, Al, Mn, and Co.
 10. The display device according to claim 1, wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer.
 11. A display device provided with a display panel comprising: a pixel portion comprising a pixel, wherein the pixel comprises a liquid crystal display element and a first transistor including an oxide semiconductor layer; a driver circuit portion configured to drive the pixel portion and display an image on a screen; and a switching element comprising a second transistor including the oxide semiconductor layer, wherein the oxide semiconductor layer comprises a crystal, wherein a c-axis of the crystal is aligned in a direction perpendicular to a surface of the oxide semiconductor layer, wherein the first transistor and the second transistor are connected to each other with the liquid crystal display element, wherein the driver circuit portion has a function to select a first operation mode and a second operation mode, wherein the first operation mode is to perform a writing operation by writing a first image signal and a second image signal to the pixel successively so as to display an image on the screen, and wherein the second operation mode is to stop a writing operation so as to maintain one image written to the screen when the a difference is not detected between the first image signal and the second image signal, and wherein an off current of each of the first transistor and the second transistor is lower than 10 zA/ μ m at room temperature and lower than 100 zA/ μ m at 85 ° C.
 12. The display device according to claim 11, wherein an interval between the first image signal and the second image signal written to the pixel is longer than one second when a difference is not detected between the first image signal and the second image signal.
 13. The display device according to claim 11, further comprising a lighting unit, wherein a light source of the lighting unit is a light-emitting diode or an organic electroluminescence element.
 14. The display device according to claim 11, wherein the driver circuit portion comprises a gate line driver circuit configured to transmit a signal to a gate electrode of the first transistor, and wherein the gate line driver circuit is formed over a substrate over which the pixel portion is formed.
 15. The display device according to claim 11, wherein the driver circuit portion comprises a signal line driver circuit configured to transmit a signal to a source electrode or a drain electrode of the first transistor, and wherein the signal line driver circuit is formed over a substrate over which the pixel portion is formed.
 16. The display device according to claim 9, wherein the oxide semiconductor layer is an intrinsic semiconductor or a substantially intrinsic semiconductor, and wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer.
 17. The display device according to claim 11, further comprising a storage capacitor connected to a pixel electrode, and wherein the storage capacitor is provided in parallel to a liquid crystal layer of the liquid crystal display element.
 18. The display device according to claim 11, wherein potentials of a pixel electrode and a common electrode are set in a floating state when a difference is not detected between the first image signal and the second image signal.
 19. The display device according to claim 11, wherein a thin film represented by a chemical formula of InMO₃(ZnO)_(m)(m>0, where m is not an integer) is used as the oxide semiconductor layer, and wherein M represents one or more metal elements selected from Ga, Al, Mn, and Co.
 20. The display device according to claim 11, wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer.
 21. A display device provided with a display panel comprising: a pixel portion comprising a pixel, wherein the pixel comprises a liquid crystal display element and a first transistor including an oxide semiconductor layer; a driver circuit portion configured to drive the pixel portion and display an image on a screen; and a switching element comprising a second transistor including the oxide semiconductor layer, wherein the oxide semiconductor layer comprises a crystal, wherein a c-axis of the crystal is aligned in a direction perpendicular to a surface of the oxide semiconductor layer, wherein the first transistor and the second transistor are connected to each other with the liquid crystal display element, wherein the driver circuit portion has a function to write a first image signal and a second image signal to the pixel successively so as to display an image on the screen, and a function to stop a writing operation of the second image signal and turn the first transistor off so as to maintain one image written to the screen when a difference is not detected between the first image signal and the second image signal, wherein an off current of each of the first transistor and the second transistor is lower than 10 zA/ μ m at room temperature and lower than 100 zA/ μ m at 85 ° C., and wherein a source electrode and a drain electrode of each of the first transistor and the second transistor comprise metal nitride.
 22. The display device according to claim 21, wherein an interval between the first image signal and the second image signal written to the pixel is longer than one second when a difference is not detected between the first image signal and the second image signal.
 23. The display device according to claim 21, further comprising a lighting unit, wherein a light source of the lighting unit is a light-emitting diode or an organic electroluminescence element.
 24. The display device according to claim 21, wherein the driver circuit portion comprises a gate line driver circuit configured to transmit a signal to a gate electrode of the first transistor, and wherein the gate line driver circuit is formed over a substrate over which the pixel portion is formed.
 25. The display device according to claim 21, wherein the driver circuit portion comprises a signal line driver circuit configured to transmit a signal to the source electrode or the drain electrode of the first transistor, and wherein the signal line driver circuit is formed over a substrate over which the pixel portion is formed.
 26. The display device according to claim 21, wherein the oxide semiconductor layer is an intrinsic semiconductor or a substantially intrinsic semiconductor, and wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer.
 27. The display device according to claim 21, further comprising a storage capacitor connected to a pixel electrode, and wherein the storage capacitor is provided in parallel to a liquid crystal layer of the liquid crystal display element.
 28. The display device according to claim 21, wherein the source electrode and the drain electrode of each of the first transistor and the second transistor comprise tungsten nitride, titanium nitride, or molybdenum nitride.
 29. The display device according to claim 21, wherein potentials of a pixel electrode and a common electrode are set in a floating state when a difference is not detected between the first image signal and the second image signal.
 30. The display device according to claim 21, wherein a thin film represented by a chemical formula of InMO₃(ZnO)_(m)(m>0, where m is not an integer) is used as the oxide semiconductor layer, and wherein M represents one or more metal elements selected from Ga, Al, Mn, and Co.
 31. The display device according to claim 21, wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer.
 32. A display device provided with a display panel comprising: a pixel portion comprising a pixel, wherein the pixel comprises a liquid crystal display element and a first transistor including an oxide semiconductor layer; a driver circuit portion configured to drive the pixel portion and display an image on a screen; and a switching element comprising a second transistor including the oxide semiconductor layer, wherein the oxide semiconductor layer comprises a crystal, wherein a c-axis of the crystal is aligned in a direction perpendicular to a surface of the oxide semiconductor layer, wherein the first transistor and the second transistor are connected to each other with the liquid crystal display element, wherein the driver circuit portion has a function to select a first operation mode and a second operation mode, wherein the first operation mode is to perform a writing operation by writing a first image signal and a second image signal to the pixel successively so as to display an image on the screen, and wherein the second operation mode is to stop a writing operation so as to maintain one image written to the screen when the a difference is not detected between the first image signal and the second image signal, wherein an off current of each of the first transistor and the second transistor is lower than 10 zA/ μ m at room temperature and lower than 100 zA/μ m at 85 ° C., and wherein a source electrode and a drain electrode of each of the first transistor and the second transistor comprise metal nitride.
 33. The display device according to claim 32, wherein an interval between the first image signal and the second image signal written to the pixel is longer than one second when a difference is not detected between the first image signal and the second image signal.
 34. The display device according to claim 32, further comprising a lighting unit, wherein a light source of the lighting unit is a light-emitting diode or an organic electroluminescence element.
 35. The display device according to claim 32, wherein the driver circuit portion comprises a gate line driver circuit configured to transmit a signal to a gate electrode of the first transistor, and wherein the gate line driver circuit is formed over a substrate over which the pixel portion is formed.
 36. The display device according to claim 32, wherein the driver circuit portion comprises a signal line driver circuit configured to transmit a signal to the source electrode or the drain electrode of the first transistor, and wherein the signal line driver circuit is formed over a substrate over which the pixel portion is formed.
 37. The display device according to claim 32, wherein the oxide semiconductor layer is an intrinsic semiconductor or a substantially intrinsic semiconductor, and wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer.
 38. The display device according to claim 32, further comprising a storage capacitor connected to a pixel electrode, and wherein the storage capacitor is provided in parallel to a liquid crystal layer of the liquid crystal display element.
 39. The display device according to claim 32, wherein the source electrode and the drain electrode of each of the first transistor and the second transistor comprise tungsten nitride, titanium nitride, or molybdenum nitride.
 40. The display device according to claim 32, wherein potentials of a pixel electrode and a common electrode are set in a floating state when a difference is not detected between the first image signal and the second image signal.
 41. The display device according to claim 32, wherein a thin film represented by a chemical formula of InMO₃(ZnO)m (m>0, where m is not an integer) is used as the oxide semiconductor layer, and wherein M represents one or more metal elements selected from Ga, Al, Mn, and Co.
 42. The display device according to claim 32, wherein a channel formation region of each of the first transistor and the second transistor is formed in the oxide semiconductor layer. 